C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 86

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
write/erase operations are disabled. Note that code execution in the 8051 is stalled while the Flash is
being programmed or erased.
Table 10.1. Flash Memory Electrical Characteristics
V
Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
instruction and read using the MOVC instruction.
The MCU incorporates an additional 128-byte sector of Flash memory located at 0x2000 – 0x207F. This
sector can be used for program code or data storage. However, its smaller sector size makes it particularly
well suited as general purpose, non-volatile scratchpad memory. Even though Flash memory can be writ-
ten a single byte at a time, an entire sector must be erased first. In order to change a single byte of a multi-
byte data set, the data must be moved to temporary storage. Next, the sector is erased, the data set
updated and the data set returned to the original sector. The 128-byte sector-size facilitates updating data
without wasting program memory space by allowing the use of internal data RAM for temporary storage. (A
normal 512-byte sector is too large to be stored in the 256-byte internal data memory.)
10.2. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as prevent the viewing of proprietary program code and constants. The Program Store Write
Enable (PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from
accidental modification by software. These bits must be explicitly set to logic 1 before software can modify
the Flash memory. Additional security features prevent proprietary program code and data constants from
being read or altered across the JTAG interface or by software running on the system controller.
A set of security lock bytes stored at 0x1DFE and 0x1DFF protect the Flash program memory from being
read or altered across the JTAG interface. Each bit in a security lock-byte protects one 1 kB block of mem-
ory. Clearing a bit to logic 0 in a Read lock byte prevents the corresponding block of Flash memory from
being read across the JTAG interface. Clearing a bit in the Write/Erase lock byte protects the block from
JTAG erasures and/or writes. The Read lock byte is at location 0x1DFF. The Write/Erase lock byte is
located at 0x1DFE. Figure 10.1 shows the location and bit definitions of the security bytes. The 512-byte
sector containing the lock byte cannot be erased by software. Writing to the reserved area should not be
performed.
86
Endurance
Erase/Write Cycle Time
DD
= 2.7 to 3.6 V, –40 to +85 ×C unless otherwise specified.
Parameter
Conditions
Rev. 1.6
20 k
Min
—
100 k
Typ
10
Max
—
—
Erase/Wr
Units
ms