C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 41

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

6.2.
The ADC has a maximum conversion speed of 100 ksps. The ADC conversion clock is derived from the
system clock. The ADC conversion clock is derived from a divided version of SYSCLK. Divide ratios of 1,
2, 4, 8, or 16 are supported by setting the ADCSC bits in the ADC0CF Register. This is useful to adjust
conversion speed to accommodate different system clock speeds.
A conversion can be initiated in one of two ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed "on-
demand". During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete.
The falling edge of ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag in the
ADC0CN register. Note: When conversions are performed "on-demand", the ADCINT flag, not ADBUSY,
should be polled to determine when the conversion has completed. Converted data is available in the ADC
data word register, ADC0H.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC
input is continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of
two different low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in
ADC0CN):
Tracking can be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
ADC Modes of Operation
1. Writing a 1 to the ADBUSY bit of ADC0CN;
2. A Timer 2 overflow (i.e. timed continuous conversions). 
1. Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2. Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks. 
Figure 6.2. 12-Bit ADC Track and Conversion Example Timing
Timer2, Timer3 Overflow;
(ADSTM[1:0]=00, 01, 11)
Write 1 to ADBUSY
(ADSTM[1:0]=10)
SAR Clocks
SAR Clocks
SAR Clocks
ADCTM=1
ADCTM=0
ADCTM=1
ADCTM=0
CNVSTR
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
Track or Convert
Low Power or
Low Power or
Convert
Convert
Track Or Convert
1
1
Track
2
2
Track
3
3
4
4
1
5
5
2
6
6
Rev. 1.6
3
7
7
Convert
4
8
8
5
9
9
10 11 12 13 14 15 16 17 18 19
10 11 12 13 14 15 16
6
Convert
7
Convert
Convert
8
9
10 11 12 13 14 15 16
Low Power Mode
Track
Low Power Mode
C8051F2xx
Track
41