C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 141

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

Bit15
This register determines how the Flash interface logic will respond to reads and writes to the FLASH-
Bits7–4: WRMD3–0: Write Mode Select Bits.
Bits3–0: RDMD3–0: Read Mode Select Bits.
This register holds the address for all JTAG Flash read, write, and erase operations. This register
autoincrements after each read or write, regardless of whether the operation succeeded or failed.
Bits15–0: Flash Operation 16-bit Address.
WRMD3
Bit7
JTAG Register Definition 18.3. FLASHADR: JTAG Flash Address
JTAG Register Definition 18.2. FLASHCON: JTAG Flash Control
DAT Register.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
0000:
0001:
0010:
(All other values for WRMD3–0 are reserved.)
The Read Mode Select Bits control how the interface logic responds to reads to the FLASH-
DAT Register per the following values:
0000:
0001:
0010:
(All other values for RDMD3–0 are reserved.)
WRMD2
Bit6
A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
ignored.
A FLASHDAT write initiates a write of FLASHDAT into the memory address selected
by the FLASHADR register. FLASHADR is incremented by one when complete.
A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
containing the address in FLASHADR. FLASHDAT must be 0xA5 for the erase to
occur. FLASHADR is not affected. If FLASHADR = 0x1DFE – 0x1DFF, the entire
user space will be erased (i.e. entire Flash memory except for Reserved area
0x1E00 – 0x1FFF).
A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise
ignored.
A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register
if no operation is currently active. This mode is used for block reads.
A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)
without initiating an extra read.
WRMD1
Bit5
WRMD0
Bit4
RDMD3
Rev. 1.6
Bit3
RDMD2
Bit2
RDMD1
Bit1
C8051F2xx
RDMD0
Bit0
Bit0
Reset Value
Reset Value
00000000
0x0000
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