EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 112

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output Control
6.5.7.3
6.5.7.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
112
PTGPE[5:0]
PTGSE[5:0]
Reset:
Reset:
Field
Field
5:0
5:0
rate control to the desired value to ensure correct operation.
W
W
R
R
Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
Port G Pull Enable Register (PTGPE)
0
0
Port G Slew Rate Enable Register (PTGSE)
0
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 6-44. Internal Pull Enable for Port G Register (PTGPE)
Figure 6-45. Slew Rate Enable for Port G Register (PTGSE)
0
0
0
0
6
6
Table 6-42. PTGPE Register Field Descriptions
Table 6-43. PTGSE Register Field Descriptions
PTGPE5
PTGSE5
MC9S08DZ60 Series Data Sheet, Rev. 4
0
0
5
5
PTGPE4
PTGSE4
NOTE
0
0
4
4
Description
Description
PTGPE3
PTGSE3
3
0
3
0
PTGPE2
PTGSE2
0
0
2
2
PTGPE1
PTGSE1
Freescale Semiconductor
0
0
1
1
PTGPE0
PTGSE0
0
0
0
0