EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 239

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.14 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
12.3.15 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Reset:
Reset
Figure 12-19. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
W
W
R
R
TXERR7
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
AC7
0
7
0
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Filter”).
Figure 12-18. MSCAN Transmit Error Counter (CANTXERR)
TXERR6
= Unimplemented
AC6
0
6
6
0
MC9S08DZ60 Series Data Sheet, Rev. 4
TXERR5
AC5
0
5
0
5
TXERR4
NOTE
AC4
0
4
4
0
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
TXERR3
AC3
0
0
3
3
TXERR2
AC2
2
0
2
0
TXERR1
AC1
Section 12.4.1,
0
Section 12.5.3,
1
0
1
TXERR0
AC0
0
0
0
0
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