EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 232

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
1
2
12.3.6
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
232
RSTATE[1:0]
TSTATE[1:0]
WUPIE and WUPE (see
mechanism from stop or wait is required.
Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the
only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,
the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see
Flag Register
WUPIE
CSCIE
OVRIE
RXFIE
Field
5:4
3:2
7
6
1
0
1
MSCAN Transmitter Flag Register (CANTFLG)
Wake-Up Interrupt Enable
0 No interrupt request is generated from this event.
1 A wake-up event causes a Wake-Up interrupt request.
CAN Status Change Interrupt Enable
0 No interrupt request is generated from this event.
1 A CAN Status Change event causes an error interrupt request.
Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state
changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to
indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by receiver state changes.
01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state
10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”
11 Generate CSCIF interrupt on all state changes.
Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter
state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags
continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by transmitter state changes.
01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter
10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other
11 Generate CSCIF interrupt on all state changes.
Overrun Interrupt Enable
0 No interrupt request is generated from this event.
1 An overrun event causes an error interrupt request.
Receiver Full Interrupt Enable
0 No interrupt request is generated from this event.
1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
(CANRFLG)”).
changes for generating CSCIF interrupt.
receiver state changes for generating CSCIF interrupt.
state changes for generating CSCIF interrupt.
transmitter state changes for generating CSCIF interrupt.
Section 12.3.1, “MSCAN Control Register 0
Table 12-10. CANRIER Register Field Descriptions
MC9S08DZ60 Series Data Sheet, Rev. 4
Description
(CANCTL0)”) must both be enabled if the recovery
Section 12.3.4.1, “MSCAN Receiver
2
Freescale Semiconductor
state. Discard other