EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 141

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.2
Freescale Semiconductor
EREFSTEN
ERCLKEN
RANGE
EREFS
Field
BDIV
HGO
7:6
LP
5
4
3
2
1
0
Reset:
W
R
MCG Control Register 2 (MCGC2)
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits in the
MCGC1 register. This controls the bus frequency.
00
01
10
11
Frequency Range Select — Selects the frequency range for the external oscillator or external clock source.
1 High frequency range selected for the external oscillator of 1 MHz to 16 MHz (1 MHz to 40 MHz for external
0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz (32 kHz to 1 MHz for external
High Gain Oscillator Select — Controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
Low Power Select — Controls whether the FLL (or PLL) is disabled in bypassed modes.
1 FLL (or PLL) is disabled in bypass modes (lower power)
0 FLL (or PLL) is not disabled in bypass modes.
External Reference Select — Selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
External Reference Enable — Enables the external reference clock for use as MCGERCLK.
1 MCGERCLK active
0 MCGERCLK inactive
External Reference Stop Enable — Controls whether or not the external reference clock remains enabled when
the MCG enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, or
0 External reference clock is disabled in stop
clock source)
clock source)
BLPE mode before entering stop
Encoding 0 — Divides selected clock by 1
Encoding 1 — Divides selected clock by 2 (reset default)
Encoding 2 — Divides selected clock by 4
Encoding 3 — Divides selected clock by 8
0
7
BDIV
Table 8-2. MCG Control Register 2 Field Descriptions
1
6
Figure 8-4. MCG Control Register 2 (MCGC2)
MC9S08DZ60 Series Data Sheet, Rev. 4
RANGE
5
0
HGO
0
4
Description
.
Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
LP
0
3
EREFS
0
2
ERCLKEN EREFSTEN
0
1
0
0
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