EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 86
EVB9S08DZ60
Manufacturer Part Number
EVB9S08DZ60
Description
BOARD EVAL FOR 9S08DZ60
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(2 pages)
3.EVB9S08DZ60.pdf
(32 pages)
4.EVB9S08DZ60.pdf
(13 pages)
5.EVB9S08DZ60.pdf
(4 pages)
Specifications of EVB9S08DZ60
Contents
Module and Misc Hardware
Processor To Be Evaluated
S08D
Data Bus Width
8 bit
Interface Type
RS-232, USB
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08D
Kit Contents
Board Cables CD Power Supply
Rohs Compliant
Yes
For Use With/related Products
MC9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EVB9S08DZ60
Manufacturer:
TI
Quantity:
101
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Chapter 6 Parallel Input/Output Control
In general, whenever a pin is shared with both an alternate digital function and an analog function, the
analog function has priority such that if both the digital and analog functions are enabled, the analog
function controls the pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.2
Associated with the parallel I/O ports is a set of registers located in the high page register space that operate
independently of the parallel I/O registers. These registers are used to control pull-ups, slew rate, and drive
strength for the pins.
An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up
enable register (PTxPEn). The pull-up device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pull-up
enable register bit. The pull-up device is also disabled if the pin is controlled by an analog function.
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
86
Pull-up, Slew Rate, and Drive Strength
Slew rate reset default values may differ between engineering samples and
final production parts. Always initialize slew rate control to the desired
value to ensure correct operation.
Port Read
BUSCLK
Data
Figure 6-1. Parallel I/O Block Diagram
MC9S08DZ60 Series Data Sheet, Rev. 4
PTxDDn
D
D
PTxDn
Q
Q
NOTE
1
0
Synchronizer
Output Enable
Output Data
Freescale Semiconductor
Input Data
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