EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 80

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
2
Chapter 5 Resets, Interrupts, and General System Control
5.8.4
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. This register should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
80
COPT[1:0]
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
Values shown in milliseconds based on t
tolerance of this value.
Reset:
SCI2PS
STOPE
COPCLKS
IICPS
Field
7:6
5
4
3
W
N/A
R
0
0
0
1
1
1
Control Bits
System Options Register 1 (SOPT1)
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
SCI2 Pin Select— This write-once bit selects the location of the RxD2 and TxD2 pins of the SCI2 module.
0 TxD2 on PTF0, RxD2 on PTF1.
1 TxD2 on PTE6, RxD2 on PTE7.
IIC Pin Select— This write-once bit selects the location of the SCL and SDA pins of the IIC module.
0 SCL on PTF2, SDA on PTF3.
1 SCL on PTE4, SDA on PTE5.
1
7
COPT
COPT[1:0]
= Unimplemented or Reserved
0:0
0:1
1:0
1:1
0:1
1:0
1:1
1
6
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Clock Source
Table 5-6. COP Configuration Options
LPO
MC9S08DZ60 Series Data Sheet, Rev. 4
STOPE
1 kHz
1 kHz
1 kHz
0
N/A
Bus
Bus
Bus
5
= 1 ms. See t
SCI2PS
COP Window
LPO
0
4
196,608 cycles
49,152 cycles
Description
(COPW = 1)
6144 cycles
in the appendix
N/A
N/A
N/A
N/A
IICPS
1
Table
Opens
3
0
5-6.
Section A.12.1, “Control
0
0
2
COP Overflow Count
2
2
2
10
8
5
COP is disabled
cycles (256 ms
cycles (32 ms
cycles (1.024 s
2
2
2
Freescale Semiconductor
13
16
18
cycles
cycles
cycles
0
0
1
Timing,” for the
2
1
1
)
)
)
0
0
0