EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 269

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.5.7.1
The MSCAN supports four interrupt vectors (see
(for details see sections from
to
12.5.7.2
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXEx flag of the empty message buffer is set.
12.5.7.3
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO.
This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are
multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the
foreground buffer.
12.5.7.4
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN internal sleep mode.
WUPE (see
12.5.7.5
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition
occurrs.
conditions:
Freescale Semiconductor
Section 12.3.7, “MSCAN Transmitter Interrupt Enable Register
•
•
Overrun — An overrun condition of the receiver FIFO as described in
Structures,” occurred.
CAN Status Change — The actual value of the transmit and receive error counters control the
CAN bus state of the MSCAN. As soon as the error counters skip into a critical range
(Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change,
which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
Section 12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)
Section 12.3.1, “MSCAN Control Register 0
Wake-Up Interrupt (WUPIF)
Error Interrupts Interrupt (CSCIF, OVRIF)
Receive Interrupt (RXF)
Transmit Interrupts (TXE[2:0])
Description of Interrupt Operation
Transmit Interrupt
Receive Interrupt
Wake-Up Interrupt
Error Interrupt
The dedicated interrupt vector addresses are defined in the
Interrupts
Interrupt Source
chapter.
Section 12.3.5, “MSCAN Receiver Interrupt Enable Register
MC9S08DZ60 Series Data Sheet, Rev. 4
Table 12-37. Interrupt Vectors
NOTE
Table
CCR Mask
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
12-37), any of which can be individually masked
I bit
I bit
I bit
I bit
(CANCTL0)”) must be enabled.
CANRIER (WUPIE)
CANRIER (CSCIE, OVRIE)
CANRIER (RXFIE)
CANTIER (TXEIE[2:0])
(CANTIER)”).
Local Enable
Resets and
indicates one of the following
Section 12.5.2.3, “Receive
(CANRIER),”
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