EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 250

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
Section 12.3.1, “MSCAN Control Register 0
read the time stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Read: Anytime when TXEx flag is set (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register
Write: Unimplemented
12.5
12.5.1
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
250
Reset:
Reset:
W
W
Functional Description
R
R
General
TSR15
TSR7
7
x
7
x
Figure 12-36. Time Stamp Register — High Byte (TSRH)
Figure 12-37. Time Stamp Register — Low Byte (TSRL)
TSR14
TSR6
6
x
6
x
MC9S08DZ60 Series Data Sheet, Rev. 4
TSR13
TSR5
5
x
5
x
Section 12.3.6, “MSCAN Transmitter Flag Register
(CANCTL0)”). In case of a transmission, the CPU can only
(CANTBSEL)”).
TSR12
TSR4
4
x
4
x
TSR11
TSR3
x
x
3
3
TSR10
TSR2
2
x
2
x
Freescale Semiconductor
TSR9
TSR1
Section 12.3.10,
x
x
1
1
TSR8
TSR0
0
x
0
x