EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 213

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.4.2
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of
read/write formats are possible within a transfer that includes 10-bit addressing.
11.4.2.1
The transfer direction is not changed (see
each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own
address and tests whether the eighth bit (R/W direction bit) is 0. More than one device can find a match
and generate an acknowledge (A1). Then, each slave that finds a match compares the eight bits of the
second byte of the slave address with its own address. Only one slave finds a match and generates an
acknowledge (A2). The matching slave remains addressed by the master until it receives a stop condition
(P) or a repeated start condition (Sr) followed by a different slave address.
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an IIC
interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this
interrupt.
11.4.2.2
The transfer direction is changed after the second R/W bit (see
acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a
slave-receiver. After the repeated start condition (Sr), a matching slave remembers that it was addressed
before. This slave then checks whether the first seven bits of the first byte of the slave address following
Sr are the same as they were after the start condition (S) and tests whether the eighth (R/W) bit is 1. If there
is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge A3.
The slave-transmitter remains addressed until it receives a stop condition (P) or a repeated start condition
(Sr) followed by a different slave address.
After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first byte
of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are
addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not
match.
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC
interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this
interrupt.
Freescale Semiconductor
S
11110 + AD10 + AD9
Slave Address
1st 7 bits
S
10-bit Address
Table 11-10. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
Slave Address 1st 7 bits
Master-Transmitter Addresses a Slave-Receiver
Table 11-9. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address
Master-Receiver Addresses a Slave-Transmitter
11110 + AD10 + AD9
R/W
0
A1
Slave Address
R/W
2nd byte
AD[8:1]
0
MC9S08DZ60 Series Data Sheet, Rev. 4
A1
Table
Slave Address 2nd byte
A2
11-9). When a 10-bit address follows a start condition,
Sr
AD[8:1]
11110 + AD10 + AD9
Slave Address
1st 7 bits
Table
A2
Data
Chapter 11 Inter-Integrated Circuit (S08IICV2)
11-10). Up to and including
R/W
1
A
A3
...
Data
Data
A
A/A
...
Data
P
A
213
P