EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 50

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
0x1883
0x1884
0x1885
0x1886
0x1887
0x1888
0x1889
0x188A
0x188B
0x188C
0x188D
0x188E
0x188F
0x1890 –
0x1893
0x1894 –
0x1897
0x1898 –
0x189B
0x189C–
0x189F
0x18BE
0x18BF
0x18C0–
0x18FF
0x18A0
0x18A1
0x18A2
0x18A3
0x18A4 –
0x18AB
0x18AC
0x18AD
0x18AE
Chapter 4 Memory
Figure 4-4
registers vary depending on whether standard or extended mapping is selected. See
Controller Area Network
50
Address
This bit is reserved. User must write a 1 to this bit. Failing to do so may result in unexpected behavior.
Table 4-4. MSCAN Foreground Receive and Transmit Buffer Layouts — Extended Mapping Shown
CANBTR1
CANRFLG
CANRIER
CANTFLG
CANTIER
CANTARQ
CANTAAK
CANTBSEL
CANIDAC
Reserved
CANMISC
CANRXERR
CANTXERR
CANIDAR0 –
CANIDAR3
CANIDMR0 –
CANIDMR3
CANIDAR4 –
CANIDAR7
CANIDMR4 –
CANIDMR7
CANTTSRH
CANTTSRL
Reserved
CANRIDR0
CANRIDR1
CANRIDR2
CANRIDR3
CANRDSR0 –
CANRDSR7
CANRDLR
Reserved
CANRTSRH
Register Name
shows the structure of receive and transmit buffers for extended identifier mapping. These
Table 4-3. High-Page Register Summary (Sheet 3 of 3)
(S08MSCANV1),” for details on extended and standard identifier mapping.
RXERR7
TXERR7
WUPIF
WUPIE
TSR15
TSR15
SAMP
TSR7
Bit 7
AM7
AM7
ID28
ID20
ID14
AC7
AC7
DB7
ID6
—
—
—
—
0
0
0
0
0
0
0
0
MC9S08DZ60 Series Data Sheet, Rev. 4
RXERR6
TXERR6
TSEG22
TSR14
TSR14
CSCIF
CSCIE
TSR6
AM6
AM6
ID27
ID19
ID13
AC6
AC6
DB6
ID5
—
—
—
—
6
0
0
0
0
0
0
0
0
RSTATE1
RXERR5
TXERR5
TSEG21
RSTAT1
IDAM1
TSR13
TSR13
TSR5
ID26
ID18
ID12
AM5
AM5
AC5
AC5
DB5
ID4
—
—
—
—
5
0
0
0
0
0
0
0
RSTATE0
RXERR4
TXERR4
TSEG20
RSTAT0
SRR
TSR12
TSR12
IDAM0
TSR4
AM4
AM4
ID25
ID11
AC4
AC4
DB4
ID3
—
—
—
—
4
0
0
0
0
0
0
0
(1)
TSTATE1
RXERR3
TXERR3
TSEG13
TSTAT1
TSR11
TSR11
IDE
TSR3
DLC3
ID24
ID10
AM3
AM3
DB3
AC3
AC3
ID2
—
—
—
3
0
0
0
0
0
0
0
0
(1)
TSTATE0
ABTRQ2
RXERR2
TSEG12
TXERR2
ABTAK2
TSTAT0
TXEIE2
IDHIT2
TSR10
TSR10
TSR2
DLC2
TXE2
ID23
ID17
AM2
AM2
AC2
AC2
DB2
TX2
ID9
ID1
—
—
—
2
0
0
Chapter 12, “Freescale
Freescale Semiconductor
RXERR1
ABTRQ1
TXERR1
TSEG11
ABTAK1
TXEIE1
IDHIT1
OVRIF
OVRIE
DLC1
TXE1
TSR9
TSR1
TSR9
AM1
AM1
ID22
ID16
AC1
AC1
DB1
TX1
ID8
ID0
—
—
—
1
0
0
BOHOLD
ABTRQ0
RXERR0
TXERR0
TSEG10
ABTAK0
TXEIE0
IDHIT0
RXFIE
TXE0
TSR8
TSR0
DLC0
TSR8
RTR
Bit 0
ID21
ID15
RXF
AM0
AM0
TX0
AC0
AC0
DB0
ID7
—
—
—
0
2