EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 216

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.7
216
1.
2.
3.
4.
5.
1.
2.
3.
4.
5.
6.
7.
Write: IICC2
— to enable or disable general call
— to select 10-bit or 7-bit addressing mode
Write: IICA
— to set the slave address
Write: IICC1
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in
Write: IICF
— to set the IIC baud rate (example provided in this chapter)
Write: IICC1
— to enable IIC and interrupts
Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data
Initialize RAM variables used to achieve the routine shown in
Write: IICC1
— to enable TX
Write: IICC1
— to enable MST (master mode)
Write: IICD
— with the address of the target slave. (The lsb of this byte determines whether the communication is
The routine shown in
incoming IIC message that contains the proper address begins IIC communication. For master operation,
communication must be initiated by writing to the IICD register.
Initialization/Application Information
IICC1
IICC2 GCAEN ADEXT
IICD
IICA
IICF
IICS
master receive or transmit.)
When addressed as a slave (in slave mode), the module responds to this address
Baud rate = BUSCLK / (2 x MULT x (SCL DIVIDER))
Module configuration
Module status flags
Data register; Write to transmit IIC data read to read IIC data
Address configuration
IICEN
TCF
MULT
Figure 11-12
IAAS
IICIE
BUSY
Figure 11-11. IIC Module Quick Start
MST
MC9S08DZ60 Series Data Sheet, Rev. 4
Module Initialization (Master)
0
Module Initialization (Slave)
can handle both master and slave IIC operations. For slave operation, an
Register Model
Module Use
ARBL
TX
AD[7:1]
0
DATA
TXAK
0
0
ICR
Figure 11-12
Figure 11-12
RSTA
SRW
AD10
IICIF
AD9
0
RXAK
AD8
0
0
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