EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 39

BOARD EVAL FOR 9S08DZ60

EVB9S08DZ60

Manufacturer Part Number
EVB9S08DZ60
Description
BOARD EVAL FOR 9S08DZ60
Manufacturer
Freescale Semiconductor
Type
MCUr

Specifications of EVB9S08DZ60

Contents
Module and Misc Hardware
Processor To Be Evaluated
S08D
Data Bus Width
8 bit
Interface Type
RS-232, USB
Silicon Manufacturer
Freescale
Core Architecture
HCS08
Core Sub-architecture
HCS08
Silicon Core Number
MC9S08
Silicon Family Name
S08D
Kit Contents
Board Cables CD Power Supply
Rohs Compliant
Yes
For Use With/related Products
MC9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EVB9S08DZ60
Manufacturer:
TI
Quantity:
101
To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the user
must restore the contents of the I/O port registers, which have been saved in RAM, to the port registers
before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to
PPDACK, then the pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.3
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Mode” and
Freescale Semiconductor
On-Chip Peripheral Modules in Stop Modes
Section 3.6.1, “Stop3 Mode
1
2
3
4
CPU
RAM
Flash/EEPROM
Parallel Port Registers
ACMP
ADC
IIC
MCG
MSCAN
RTC
SCI
SPI
TPM
Voltage Regulator
XOSC
I/O Pins
BDM
LVD/LVW
Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
IRCLKEN and IREFSTEN set in MCGC1, else in standby.
Requires the RTC to be enabled, else in standby.
Requires the LVD or BDC to be enabled.
Peripheral
MC9S08DZ60 Series Data Sheet, Rev. 4
Table 3-2. Stop Mode Behavior
” for specific information on system behavior in stop modes.
Optionally On
States Held
Standby
Stop2
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
6
7
3
Mode
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
Optionally On
States Held
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Standby
Stop3
Off
Chapter 3 Modes of Operation
Section 3.6.2, “Stop2
1
2
3
4
5
39

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