EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 120

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Central Processor Unit (S08CPUV3)
7.3.5
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
7.3.6
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and
two that use the stack pointer as the base reference.
7.3.6.1
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
7.3.6.2
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.
7.3.6.3
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.4
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
7.3.6.5
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.6
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
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Extended Addressing Mode (EXT)
Indexed Addressing Mode
Indexed, No Offset (IX)
Indexed, No Offset with Post Increment (IX+)
Indexed, 8-Bit Offset (IX1)
Indexed, 8-Bit Offset with Post Increment (IX1+)
Indexed, 16-Bit Offset (IX2)
SP-Relative, 8-Bit Offset (SP1)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor