EVB9S08DZ60 Freescale Semiconductor, EVB9S08DZ60 Datasheet - Page 183

• Manufacturer Part Number: EVB9S08DZ60
• Description: BOARD EVAL FOR 9S08DZ60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S08DZ60

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: S08D
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: Board Cables CD Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]).
These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the
compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.
10.3.6
This register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare
value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower 8 bits of the
result following a conversion in 12-bit, 10-bit or 8-bit mode.
10.3.7
Freescale Semiconductor
ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and
long sample time.
ADLSMP
ADLPC
Field
ADIV
6:5
7
4
Reset:
Reset:
W
W
R
R
Compare Value Low Register (ADCCVL)
Configuration Register (ADCCFG)
Low-Power Configuration. ADLPC controls the speed and power configuration of the successive approximation
converter. This optimizes power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: The power is reduced at the expense of maximum clock speed.
Clock Divide Select. ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
Table 10-7
Long Sample Time Configuration. ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
ADCV7
ADLPC
7
0
7
0
shows the available clock configurations.
ADCV6
Figure 10-8. Compare Value Low Register (ADCCVL)
Table 10-6. ADCCFG Register Field Descriptions
0
0
6
6
Figure 10-9. Configuration Register (ADCCFG)
ADIV
MC9S08DZ60 Series Data Sheet, Rev. 4
ADCV5
0
0
5
5
ADLSMP
ADCV4
0
0
4
4
Description
ADCV3
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
0
0
3
3
MODE
ADCV2
0
0
2
2
ADCV1
0
0
1
1
ADICLK
ADCV0
0
0
0
0
183