MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet

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MCF5253 Reference Manual Document Number: MCF5253RM Rev. 1 08/2008 ...

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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...

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... JTAG 1-12 1.5.28 System Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5.29 System Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5.30 Sleep and Wake-Up Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.5.31 Bootloader 1-13 1.5.32 Internal Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Chapter 2 Signal Description 2.1 Overview 2-1 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 iii ...

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... Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.25.1 Reset 2-14 2.25.2 System Bus Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.26 Wake-Up Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.27 On-Chip Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Chapter 3 ColdFire Core 3.1 Processor Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 ColdFire Processor Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 iv MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... PLL Features 4-1 4.2 PLL Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.2 PLL Lock-In Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.3 PLL Electrical Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3 Dynamic Clock Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4 Audio Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Freescale Semiconductor MCF5253 Reference Manual, Rev ...

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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 Synchronous Operation 7-2 7.2.1 DRAM Controller Signals in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 SDRAM Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3.1 DRAM Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3.1.1 DRAM Control Register (DCR) (Synchronous Mode 7-4 vi MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.4 Back-to-Back Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.5 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.5.5.1 Line Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.5.5.2 Line Read Bus Cycles 8-10 8.6 Misaligned Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.7 Reset Operation 8-14 8.7.1 Software Watchdog Reset 8-15 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 vii ...

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... General Purpose Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.9 Multiplexed Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 Chapter 10 Chip Select Module 10.1 Chip Select Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 Chip Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2.1 CS0/CS4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2.2 CS1/QSPI_CS3/GPIO28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2.3 CS2 — IDE_DIOR/GPIO31 and IDE_DIOW/GPIO32 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 viii MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Analog to Digital Converter (ADC) 12.1 Overview 12-1 12.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.3 ADC Memory Map and Register Definitions 12-2 12.3.1 AD Configuration Register (ADconfig 12-2 12.3.2 AD Value Register (ADvalue 12-3 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Freescale Semiconductor MCF5253 Reference Manual, Rev ...

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... DMA Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2.1 DMA Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.3 DMA Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.4 DMA Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.4.1 REQUEST Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.4.2 Source Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.4.3 Destination Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 x MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Calculating Baud Rates 15-5 15.3.2 Transmitter and Receiver Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.3.2.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.2.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.3.2.3 Receiver FIFO 15-9 15.3.3 Looping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.3.3.1 Automatic Echo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.3.3.2 Local Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Freescale Semiconductor MCF5253 Reference Manual, Rev ...

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... Interrupt Vector Registers (UIVRn 15-27 15.4.15 Input Port Registers (UIPn 15-27 15.4.16 Output Port Data Registers (UOP1n 15-28 15.4.17 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 15.4.17.1 UART Module Initialization 15-29 15.4.17.2 I/O Driver Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 15.4.17.3 Interrupt Handling 15-29 xii MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Digital Audio Interface (EBU/SPDIF) Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17.6.1 IEC958 Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.6.1.1 Audio Data Reception 17-16 17.6.1.2 Control Channel Reception Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.6.1.3 Control Channel Interrupt (IEC958 “C” Channel New Frame 17-17 Freescale Semiconductor 2 S/EIAJ) Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 MCF5253 Reference Manual, Rev. 1 xiii ...

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... Incoming Source Frequency Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42 17.9.1.1 Filtering for the Discrete Time Oscillator 17-44 17.9.2 XTRIM Option - Locking Xtal Clock to Incoming Signal 17-44 17.9.3 XTRIM Internal Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-45 Chapter Modules 18.1 I2C Interface Features 18 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 xiv MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Supported Commands 19-5 19.2.4 IDE Boot Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.2.5 Boot Modes 19-5 2 19.2.5.1 Boot From SPI – Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 2 19.2.5.2 Boot from Slave Mode 19-6 19.2.5.3 Boot from UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.2.5.3.1 UART Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 Freescale Semiconductor MCF5253 Reference Manual, Rev ...

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... Read Memory Location (READ 20-14 20.3.4.1.4 Write Memory Location (WRITE 20-16 20.3.4.1.5 Dump Memory Block (DUMP 20-17 20.3.4.1.6 Fill Memory Block (FILL 20-19 20.3.4.1.7 Resume Execution (GO 20-21 20.3.4.1.8 No Operation (NOP 20-21 20.3.4.1.9 Read Control Register (RCREG 20-22 xvi MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... SAMPLE/PRELOAD Instruction 21-7 21.5.1.4 CLAMP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.5.1.5 HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.5.1.6 BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.5.2 ID Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.5.3 JTAG Boundary Scan Register 21-9 21.5.4 JTAG Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.6 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 xvii ...

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... PIO Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.3.3 Timing in Multiword DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.4.3.4 UDMA In Timing Diagrams 23-10 23.4.3.5 UDMA Out Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.5 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 23.5.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15 23.5.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 xviii MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Programming ATA Bus Timing and iordy_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-33 23.6.3 Access to ATA Bus in PIO Mode 23-33 23.6.4 Using DMA Mode to Receive Data from ATA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-34 23.6.5 Using DMA Mode to Transmit Data to ATA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-35 Chapter 24 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 xix ...

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... USB Mode Register (USBMODE)—Non-EHCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-37 24.6.3.16 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI . . . . . . . . . . . 24-38 24.6.3.17 Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI . . . . . . . . . . . . . . . . 24-39 24.6.3.18 Endpoint Flush Register (ENDPTFLUSH), Non-EHCI 24-40 24.6.3.19 Endpoint Status Register (ENDPTSTATUS), Non-EHCI . . . . . . . . . . . . . . . . . . . . . 24-41 xx MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries . . . . . . . . . . . . . . . . . . 24-72 24.9.7 Periodic Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-74 24.9.8 Managing Isochronous Transfers Using iTDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-75 24.9.8.1 Host Controller Operational Model for iTDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-75 24.9.8.2 Software Operational Model for iTDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-77 24.9.8.2.1 Periodic Scheduling Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-78 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 xxi ...

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... Data Buffer Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-119 24.9.14.1.4 USB Interrupt (Interrupt on Completion (IOC)). . . . . . . . . . . . . . . . . . . . . . . . . 24-120 24.9.14.1.5 Short Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120 24.9.14.2 Host Controller Event Interrupts 24-120 24.9.14.2.1 Port Change Events 24-120 24.9.14.2.2 Frame List Rollover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120 24.9.14.2.3 Interrupt on Async Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-120 xxii MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Managing Transfers with Transfer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-143 24.11.5.1 Software Link Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-143 24.11.5.2 Building a Transfer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-144 24.11.5.3 Executing A Transfer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-144 24.11.5.4 Transfer Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-145 24.11.5.5 Flushing/De-Priming an Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-146 24.11.5.6 Device Error Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-146 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 xxiii ...

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... Listen-only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.4 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.5 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.5.1 FlexCAN Configuration Register (CANMCRn 25-6 25.5.2 FlexCAN Control Register (CANCTRLn 25-8 25.5.3 FlexCAN Free Running Timer Register (TIMERn 25-11 xxiv MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.3 Memory Map and Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.3.1 Miscellaneous Configuration Register (MISCCR 26-2 26.3.2 RTC Time Register (RTC_TIME 26-2 26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.4.1 Battery Removal Detection 26-2 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 xxv ...

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... MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Bus operation is defined for transfers initiated by the MCF5253 as a bus master and for transfers initiated by an alternate Freescale Semiconductor This chapter provides an overview of the MCF5253 ColdFire® This chapter describes the MCF5253 input and output signals, organized Dividers” ...

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... This chapter provides the DMA signal descriptions, memory map, This chapter provides signal descriptions, operation, memory map, Module”: (AIM)”:This chapter discusses the audio interface structure, Interface”: This chapter details the MCF5253 hardware MCF5253 Reference Manual, Rev. 1 This chapter describes the operation of 2 Freescale Semiconductor C ...

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... PowerPC AIX Version 4 Application Binary Interface, 1st ed., April 1992. The KornShell Command and Programming Language, Morris Bolsky and David Korn (Prentice Hall: 1989). Freescale Semiconductor (JTAG)”: This chapter discussed the JTAG signal Module”:This chapter includes the memory map, (ATA)” ...

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... PowerPC Virtual Environment Architecture, Book II, Version 1.00, 5/19/92 (subtitled “Work in Progress”) Register Summary Figure 1 shows the key to the register fields and xxx indicate commands, command parameters, code examples, expressions, Table 2 shows the register figure conventions. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Self-clearing bit. Writing a one has some effect on the module, but it always reads as zero. 0 Resets to zero. 1 Resets to one. — Undefined at reset. u Unaffected by reset. [signal_name] Reset value is determined by polarity of indicated signal. Freescale Semiconductor BIT Read- BIT Write- bit only bit only bit BIT Figure 1. Key to Register Fields Table 2 ...

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... MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... Digital audio transmitter (SPDIF) and two receivers compliant with IEC958 audio protocol • Queued serial peripheral interface (QSPI) (master only) • CD-ROM and CD-ROM XA block decoding and encoding function Philips proprietary bus Freescale Semiconductor ® processor and general descriptions of the MCF5253 Reference Manual, Rev. 1 1-1 ...

Page 34

... General Purpose I/O pins shared with other functions • 1.2 V core, 3.3 V I/O • Internal 1.2 V Linear regulator to power the core (configuration is optional) • 225 pin MAPBGA package 1.3 MCF5253 Block Diagram Figure 1-1 provides the block diagram of the MCF5253 device. 1-2 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 35

... MHz KRAM1 64K KRAM0 “Backdoor” Interface FlexCAN Pins 2x FlexCAN Controller CRIN/CROUT Pins Oscillator RTC Pins Real-Time 16 Kbyte ARB SRAM DMA Freescale Semiconductor Standard ColdFire Peripheral Blocks Timer 5x08 DMA UART (3) 5x08 5x08 Interrupt Arbiter E-bus SDRAM Interface E-bus ...

Page 36

... Non-blocking cache provides fast access to critical code and data • 128-Kbyte SRAM — Provides one-cycle access to critical code and data — Split into two banks, SRAM0 (64K), and SRAM1 (64K) — DMA requests to/from internal SRAM1 supported • Crystal Trim 1-4 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 37

... Programmable queue to support transfers without user intervention — Supports transfer sizes bits in 1-bit increments — Four peripheral chip-select lines for control devices — Supports Baud rates up to 17.5 Mbps at 140 MHz — Programmable delays before and after transfers Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 MCF5253 Introduction 1-5 ...

Page 38

... The device can boot from external memory or from its own internal boot ROM. If selected to boot from external memory (Flash / ROM) then CS0 is active after reset. — Programmable interrupt controller (low interrupt latency, seven external interrupt requests, programmable autovector generator) — programmable general-purpose outputs — programmable general-purpose inputs 1-6 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 39

... Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions for signed and unsigned integers plus signed, fixed-point fractional input operands. The eMAC has a single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution pipeline. Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 MCF5253 Introduction 1-7 ...

Page 40

... It operates as high speed, full speed and low speed host, and as high speed and full speed device. Host negotiation protocol (HNP) and session request protocol (SRP) are implemented with software support. A USB 2.0 high-speed compatible PHY is integrated on-chip. 1-8 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 41

... In addition to the audio interfaces, there are six CPU accessible registers connected to the audio bus. Three of these registers allow data reads from the audio bus and allow selection of the audio source. The other Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 MCF5253 Introduction ...

Page 42

... UARTs can interrupt the CPU on numerous events. 1.5.18 Queued Serial Peripheral Interface The QSPI module provides a serial peripheral interface with queued transfer capability. It supports stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers 1-10 QSPI MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 43

... Three programmable chip-select outputs (CS0/CS4, CS1 and CS2) provide signals that enable glueless connection to external memory and peripheral circuits. The base address, access permissions, and automatic wait-state insertion are programmable with configuration registers. These signals also interface to 16-bit ports. Freescale Semiconductor ® , SecureDigital and Multi-Media card compatible. However, there . ...

Page 44

... Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is intended for use when the 33.86 MHz crystal option is used. 1-12 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 45

... However, it must be noted that the internal regulator has an efficiency of less than 50%, and it is not intended for use in battery powered applications, where the use of a highly efficient external DC-DC converter would be more appropriate. Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 MCF5253 Introduction ...

Page 46

... MCF5253 Introduction 1-14 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 47

... IDE_DIOR/GPIO31 (CS2) ISA bus write strobe IDE_DIOW/GPIO32 (CS2) ISA bus wait signal IDE_IORDY/GPIO33 Freescale Semiconductor Table 2-1. MCF5253 Signal Index Mnemonic 24 address lines—address 23 is multiplexed with GPO54 and address 24 is multiplexed with A20 (SDRAM access only). Bus write enable—indicates if read or write cycle in progress ...

Page 48

... Output Out In/Out In/Out In/Out In/Out module In/Out 2 C module In/Out In Out Out In Out In Out In In/Out Out In/Out In/Out Freescale Semiconductor Reset State negated – – – – – – – – – – – – – – – – – ...

Page 49

... ATA_DIOR ATA_IORDY ATA_DMARQ ATA_DMACK ATA_INTRQ ATA_CS0 ATA_CS1 ATA_A[2:0] ATA_D[15:0] Freescale Semiconductor Mnemonic Error flag serial in C-flag serial in Audio interfaces to subcode clock Audio interfaces to subcode sync Audio interfaces to subcode data Clock trim control DAC output clocks Optional audio clock input Secure Digital command lane— ...

Page 50

... Out In Out Analog In/Out In/Out In Out In Out In In/Out In/Out In/Out In/Out In/Out In Out In In Out In Freescale Semiconductor Reset State – – – – – – – – – – – – – – – – – – – – – – ...

Page 51

... The address bus provides the address of the byte or most significant byte of the word or longword being transferred.The address lines also serve as the DRAM address pins, providing multiplexed row and column address signals. Freescale Semiconductor Mnemonic Assertion tri-states output signal pins Display of captured processor data and break-point statuses Indication of internal processor status ...

Page 52

... This pin outputs logic ‘1’ during read bus cycles. The SD_CS0/GPIO60 active-low output signal is used during synchronous mode to route directly to the chip select of a SDRAM device. The DRAM byte enables UDMQ and LDQM are driven by the SDUDQM/GPO53 and SDLDQM/GPO52 byte enable outputs. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 53

... I C bus drive the bus, they will either drive logic-0 or high-impedance. This can be accomplished with an open-drain output. Freescale Semiconductor Table 2-2. SDRAM Controller Signals Description The DRAM clock is driven by the BCLK/GPIO40 signal. The BCLKE active high output signal is used during synchronous mode to route directly to the SCKE signal of external SDRAMs ...

Page 54

... The following signals provide the external audio interface. 2-8 2 Table 2- Module Signals Description module operation. The I C module controls this signal when the bus is in master mode timing interface. Table 2-4. Serial Module Signals Description Table 2-5. Timer Module Signals Description MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 55

... I digital audio (IEC958) output. EBUOUT1 is digital audio out for consumer mode, EBUOUT2 is digital audio out for professional mode. During reset, the pin is configured as a digital audio output. Freescale Semiconductor Table 2-6. Serial Audio Interface Signals Description Table 2-7. Digital Audio Interface Signals Description MCF5253 Reference Manual, Rev ...

Page 56

... Subcode data output. This signal is a subcode data out pin. NOTE Table 2-9. Flash Memory Card Signals Clock out for both MemoryStick interfaces and for SecureDigital. Secure Digital command line. MemoryStick interface 2 data I/O. MCF5253 Reference Manual, Rev. 1 Description Description Freescale Semiconductor ...

Page 57

... The two FlexCan modules are full implementation of the Bosch CAN protocol specification 2.0B. Pin descriptions are given in Table Freescale Semiconductor Secure Digital serial data bit 0. MemoryStick interface 1 data I/O. Secure Digital serial data bit 1. MemoryStick interface 1 strobe. Secure Digital serial data bit 2. MemoryStick interface 2 strobe. ...

Page 58

... USB dm signalling line USB dp signalling line A 24 MHz X-tal needs to be connected between these 2 pins Table 2-12. Real-Time Clock (RTC) Pins Connect a real-time clock crystal (32.768 kHz) between these 2 pins. MCF5253 Reference Manual, Rev. 1 2-11. Description Table 2-12. Description Freescale Semiconductor ...

Page 59

... Freescale Semiconductor NOTE Chapter 20, “Background Debug Mode (BDM) Definition Continue execution Begin execution of an instruction Reserved Entry into user-mode Begin execution of PULSE and WDDATA instructions Begin execution of taken branch or Synch_PC Reserved MCF5253 Reference Manual, Rev. 1 ...

Page 60

... Begin 2-byte data transfer on DDATA Begin 3-byte data transfer on DDATA Begin 4-byte data transfer on DDATA 2 Exception processing Emulator mode entry exception processing Processor is stopped, waiting for interrupt 2 Processor is halted Chapter 20, “Background Debug Mode (BDM) Interface,” MCF5253 Reference Manual, Rev Freescale Semiconductor ...

Page 61

... I/O and the core. In portable solutions, this linear regulator may not be efficient enough. In this case, we would expect the 1.2 V supply to be generated externally, possibly by a highly efficient DC-DC convertor. If not used, leave pins unconnected. Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 Signal Description 2-15 ...

Page 62

... Signal Description 2-16 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 63

... The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The Instruction Fetch Pipeline (IFP) is responsible for instruction address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution Freescale Semiconductor INSTRUCTION ADDRESS IA ...

Page 64

... Registers D0–D7 are used as data registers for bit (1 bit), byte (8 bit), word (16 bit) and longword (32 bit) operations and can also be used as index registers. 3 Figure 3-2. User Memory Map MCF5253 Reference Manual, Rev Data D3 Registers Address A3 Registers Stack A7 Pointer Program PC Counter Condition CCR Code Register Freescale Semiconductor ...

Page 65

... Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic Negative condition code bit. Set if the msb of the result is set; otherwise cleared Zero condition code bit. Set if the result equals zero; otherwise cleared. Freescale Semiconductor – – ...

Page 66

... Write the contents of the MAC status register to a CPU register Write the contents of the MAC status register to the processor’s CCR register Writes a value to the MAC Mask Register Writes the contents of the MAC mask register to a CPU register MCF5253 Reference Manual, Rev. 1 Description Freescale Semiconductor ...

Page 67

... System Byte Freescale Semiconductor Mnemonic operand operand Writes the contents of accumulator 0,1 extension bytes into a CPU register Writes the contents of accumulator 2,3 extension bytes into a CPU register 19–0 MUST BE ZEROS 15– 8 7–0 ...

Page 68

... M bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request. 3-6 Description 30 –21 0000_0000_0000_0000_0000_0000_0000_0000 0x801 Figure 3-5. Vector Base Register (VBR) Section 3.5.1, “Access Error Exception,” MCF5253 Reference Manual, Rev –0 – for details. Freescale Semiconductor ...

Page 69

... Freescale Semiconductor Table 3-5. Exception Vector Assignments 1, 2 Stacked Program Counter – Initial stack pointer – Initial program counter Fault Access error Fault Address error Fault Illegal instruction Fault Divide by zero – ...

Page 70

... The first longword of the exception stack frame contains FS[3:0] VECTOR[7:0] FS[1:0] PROGRAM COUNTER[31:0] Figure 3-6. Exception Stack Frame Form Table 3-6. Format Field Encoding A7 @ 1st Instruction of Handler Original Original Original Original MCF5253 Reference Manual, Rev. 1 Assignment STATUS REGISTER Table 3-6. Format Field Freescale Semiconductor ...

Page 71

... Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. Accordingly, the PC contained in the exception stack frame merely represents the location in the program Freescale Semiconductor Table 3-7. Fault Status Encoding Definition ...

Page 72

... The single exception to this definition is the STOP instruction. When the STOP opcode is executed, the processor core waits until an unmasked interrupt request is asserted, then aborts the pipeline and initiates interrupt exception processing. 3-10 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 73

... The interrupt exception processing, with interrupt recognition and vector fetching, includes uninitialized and spurious interrupts as well as those where the requesting device supplies the 8-bit interrupt vector. Autovectoring may optionally be supported through the System Integration module (SIM). Freescale Semiconductor Chapter 20, “Background Debug Mode MCF5253 Reference Manual, Rev. 1 ...

Page 74

... The operand execution pipeline (OEP) is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or extension words. 3-12 NOTE MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 75

... The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l. Table 3-9. Move Byte and Word Execution Times Source Rx Dn 1(0/0) 1(0/1) An 1(0/0) 1(0/1) (An) 3(1/0) 3(1/1) Freescale Semiconductor Table 3-8. Misaligned Operand References Size KBUS Operations Word Byte, Byte Long Byte, Word, Byte Long Word, Word NOTE Destination (Ax) ...

Page 76

... Freescale Semiconductor ...

Page 77

... Dy,Dx 1(0/0) and.l <ea>,Rx 1(0/0) and.l Dy,<ea> – andi.l #imm,Dx 1(0/0) asl.l <ea>,Dx 1(0/0) asr.l <ea>,Dx 1(0/0) Freescale Semiconductor Effective Address (An) (An)+ -(An) (d16,An) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) – – – – – ...

Page 78

... Freescale Semiconductor #xxx – – – – – – – 1(0/0) 1(0/0) – 20(0/0) 20(0/0) – – – – – 1(0/0) 1(0/0) – ...

Page 79

... Freescale Semiconductor Effective Address (d16,An) (An) (An)+ -(An) (d16,PC) ≤ 6(1/0) ≤ 6(1/0) ≤ 6(1/0) ≤ 6(1/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) – ...

Page 80

... Backward Taken Not Taken 2(0/0) – 2(0/0) 3(0/0) Freescale Semiconductor #xxx – – 3(1/0) – #xxx – – – – – ...

Page 81

... Dynamic Clock Switching. This allows dynamic switching of the clock rate being fed to the CPU core and the system bus. This new block is controlled by a new 32-bit register called the ClockRate Register. Figure 4-1 shows the PLL module and the frequency relationships of various clock signals. Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 4-1 ...

Page 82

... A20/A24 LRCK3/AUDIOCLK/GPIO43 Table 4-1. PLL Memory Map Size Bits Name 32 PllConfig PLL configuration register MCF5253 Reference Manual, Rev. 1 ClockRate Select Glitch Free 0 Divide By CPU CORE Divider 1 CPUDIV / PSTCLK Divide SCLK By 2 MCLK1 MCLK2 AUDIOCLK Table 4-2. Description Reset 0x02020088 Freescale Semiconductor ...

Page 83

... Switch back to operational mode SLEEP 1 Switch device to Sleep mode, including stopping clocks 10 Reserved, should be cleared PLL normal operation PLLPWRDWN 1 Disable PLL to power-down mode 8–4 Input frequency (Fin) is divided by (PllDiv) to determine the PLL compare frequency. PLLDIV 3–2 VCXO output divider VCXOOUT Freescale Semiconductor CPUDIV CRSEL ...

Page 84

... CRIN/2 0 011 CRIN/2 1 000 CRIN/2 1 001 CRIN/2 1 010 CRIN/2 1 011 CRIN/3 1 100 CRIN/3 1 101 CRIN/3 1 110 CRIN/4 1 111 CRIN/4 MCF5253 Reference Manual, Rev. 1 4-3. CRIN/2 CRIN CRIN/2 CRIN CRIN/2 CRIN/3 CRIN/4 CRIN/2 CRIN/3 CRIN/4 CRIN/2 CRIN/3 Freescale Semiconductor Notes – ...

Page 85

... Due to implementation of the block, some limits apply to the PLL block. These limitations are shown in Table 4-5. Minimum Name Frequency MHz Fvcxo 200 Fcpu 0 Fin/PLLDIV 2 Freescale Semiconductor NOTE NOTE Table 4-5. PLL Electrical Limits Maximum Frequency MHz 400 PLL limitations 140 Maximum operating frequency of device 8 PLL limitations MCF5253 Reference Manual, Rev ...

Page 86

... Table 4-7. PLLCR Bit Fields pllCR Config Audiosel AUDIO_CLOCK (Bit 22) 1 CRIN 1 CRIN 1 CRIN MCF5253 Reference Manual, Rev. 1 Table 4-3 Access: User read/write Clock rate select × 255) 4-7. As the table shows, the MCLK2 MCLK1 CRIN CRIN/2 CRIN CRIN CRIN/2 CRIN/2 Freescale Semiconductor ...

Page 87

... The device can be put in a low power Sleep mode, where all internal clocks and all on-chip functions are stopped. In Sleep mode, the only block still functional is the on-chip voltage regulator. All the other analog features are put in to low-power operation and all digital functions are stopped. Freescale Semiconductor Table 4-7. PLLCR Bit Fields (continued) pllCR Config ...

Page 88

... MHz Div 11.2896 2 11.2896 3 11.2896 4 4-8 Table 4-8. Audio_Clock Selection Fields Description Table 4-7 Table 4-9. Recommended PLL Settings Vcxo Pll CRSel Div Div MCF5253 Reference Manual, Rev this section for further definition. Vcxo CPU Out Clock MHz 1 120 Freescale Semiconductor ...

Page 89

... Byte Line-Fill Buffer • Configurable Cache Miss-Fetch Algorithm 5.2 Block Diagram Figure 5-1 illustrates the block diagram for the instruction cache memory. LOCAL ADDRESS BUS Figure 5-1. Instruction Cache Block Diagram Freescale Semiconductor ® Core High-Speed Local Bus BUFFER LINE ADDRESS = ...

Page 90

... In this case, data accessed from the instruction cache is simply discarded and no external memory references are generated. If the address is not mapped into the SRAM space, the instruction cache handles the request in the normal fashion. 5-2 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 91

... With the cache enabled as defined by CACR[31], a cacheable instruction fetch that misses in both the tag memory and the line-fill buffer generates a external fetch. The size of the external fetch is determined by Freescale Semiconductor the instruction cache hardware includes a 16-byte MCF5253 Reference Manual, Rev. 1 ...

Page 92

... Table 5-2 shows the relationship between CACR bits 31 and 10 and the type of instruction fetch. 5-4 Longword Address Bits Line Line Line Line Line Longword Line Line Line MCF5253 Reference Manual, Rev. 1 Table 5-1 shows the 11 Longword Longword Line Freescale Semiconductor ...

Page 93

... Table 5-3. Memory Map of I-Cache Registers Address MOVEC with $002 MOVEC with $004 MOVEC with $005 Freescale Semiconductor Instruction cache is completely disabled; all fetches are word, longword in size All fetches are word, longword in size Fetch size is defined by Table 5-1 written into the memory array ...

Page 94

... CFRZ is asserted. 0 Normal operation 1 Freeze valid cache lines 26–25 Reserved, should be cleared. 5 CINV CFRZ CEIB DCM DBWE Figure 5-2. Cache Control Register (CACR) Description MCF5253 Reference Manual, Rev. 1 Access: User read/write DWP CLNF1 Freescale Semiconductor CLNF2 0 ...

Page 95

... The Cache Line Fill bits control the size of the memory request the cache issues to the bus controller for different CLNF initial line access offsets. Table 5-5. External Fetch Size Based on Miss Address and CLNF CLNF[1: Freescale Semiconductor Description Table 5-5 shows the fetch size. Longword Address Bits 00 01 Line Line ...

Page 96

... Match if user mode 01 Match if supervisor mode 1x Match always. Ignore user/supervisor mode 12–7 Reserved, should be cleared. 6 The Cache Mode bit defines the cache mode cacheable noncacheable Caching enabled 1 Caching disabled 5 Description MCF5253 Reference Manual, Rev. 1 Access: User read/write BWE Freescale Semiconductor ...

Page 97

... The Write Protect bit defines the write-protection attribute. If the effective memory attributes for a given access WP select the WP bit, an access error terminates any attempted write with this bit set. 0 Read and write accesses permitted 1 Only read accesses permitted 1–0 Reserved, should be cleared. Freescale Semiconductor Description MCF5253 Reference Manual, Rev. 1 Instruction Cache 5-9 ...

Page 98

... Instruction Cache 5-10 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 99

... SRAM Base Address Register The configuration information in the SRAM Base Address Register (RAMBAR[0:1]) controls the operation of the SRAM module. • There are 2 RAMBAR registers. One for SRAM0, the second for SRAM1. Freescale Semiconductor Figure 1-1 shows this concept. MCF5253 Reference Manual, Rev. 1 6-1 ...

Page 100

... MCF5253 Reference Manual, Rev. 1 Access: User read/write – – – – – – C – – – – – – Access: User read/write – – – – – – C – – – – – – Freescale Semiconductor 16 – – ...

Page 101

... These bits are useful for power management as detailed in 0 The valid bit. A hardware reset clears this bit. When set, this bit enables the SRAM module; otherwise, the V module is disabled. 0 Contents of RAMBAR are not valid 1 Contents of RAMBAR are valid Freescale Semiconductor Description Upper Bank PRI[1:2] Priority 2’b00 CPU Accesses 2’ ...

Page 102

... ASn bits associated with instruction fetches can decrease power dissipation. Additionally, if the SRAM contains only instructions, masking data accesses can reduce power dissipation. Table 6-2 shows some examples of typical RAMBAR settings. 6-4 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 103

... Table 6-2. Typical RAMBAR Setting Examples Data Contained in SRAM Both Code And Data Freescale Semiconductor Code Only Data Only MCF5253 Reference Manual, Rev. 1 Static RAM (SRAM) RAMBAR[7:0] $2B $35 $21 6-5 ...

Page 104

... Static RAM (SRAM) 6-6 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 105

... Block Diagram The basic components of the DRAM controller are shown in A[31:0] Internal Bus Memory Block 0 Hit Logic DRAM Address/Control Register 0 Figure 7-1. Synchronous DRAM Controller Block Diagram Freescale Semiconductor Figure DRAM Controller Module Address Multiplexing Page Hit Control Logic Logic and ...

Page 106

... Exit self refresh. This command is sent to the DRAM controller when DCR[IS] is cleared. WRITE Write access. 7-2 Figure 7-1, are described as follows: NOTE Table 7-1. SDRAM Commands Definition or executes; SDRAM registers and decodes row address. READ WRITE MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 107

... Bus clock output. Connects to the CLK input of SDRAMs. Figure 7-2 shows a typical signal configuration for synchronous mode. MCF5253 SD_CS0 7.3 SDRAM Memory Map and Register Definitions The memory map is shown in Table Freescale Semiconductor NOTE Description A[31:0] D[31:16] U/L DQM SDWE SDCAS SDRAS ...

Page 108

... Section 7.3.1.3, “DRAM Controller Mask Registers Reserved Reserved Figure 7-3, controls refresh logic RTIM – – – – – Description MCF5253 Reference Manual, Rev. 1 [15:8] [7:0] Reserved (DMR0)”] Access: User read/write – – – – – – Freescale Semiconductor 0 – ...

Page 109

... Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match, the address hits in the associated DRAM block. 17–16 Reserved, should be cleared. Freescale Semiconductor Description command to exit self refresh. SELFX command to the SDRAMv to put it in low-power, self-refresh ...

Page 110

... MRS 7-6 (continued) Description Parameter CASL = 00 CASL = 01 CASL = 10 CASL = 11 N/A N/A N/A N/A N/A N/A ) command. Setting IMRS generates a MRS MCF5253 Reference Manual, Rev. 1 Number of Bus Clocks command to the associated SDRAM. In MRS and PALL REFRESH command finishes. MRS Freescale Semiconductor ...

Page 111

... Write accesses to a write-protected DRAM region are compared in the chip select module for a hit hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs. Freescale Semiconductor (continued) Description ) command. The DRAM controller clears IP after the Description Example.” ...

Page 112

... MOVEC instruction or interrupt acknowledge cycle External or DMA master Any supervisor-only instruction access Any data fetched during the instruction access Any user instruction Any user data Table 7-10, and Table 7-11 provide a comprehensive, step-by-step method MCF5253 Reference Manual, Rev. 1 Access Definition Freescale Semiconductor ...

Page 113

... A21, the AP bit must be set above this, lowest we can set it is A22. So, AP must be connected to A22. Bank addresses are then A23 and above. (Bank addresses need equal address during CAS and RAS phase). The remaining 3 D-RAM ras-only address lines are connected to A9, A11 and A12. Freescale Semiconductor A13 A12 ...

Page 114

... A20 A16 A17 A18 AP A23 A21 A17 A18 A19 A22 A23 A8 A9 A11 A12 A10 A13 A10=CMD A11 BA0/A12 BA1/A13 A19 A20/A24 A21 command in the SDRAM ACTV or READ WRITE Freescale Semiconductor A24 24 – A24 A24 A14 A22 PALL ...

Page 115

... RCD Data is available upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read cycle with the same t cycle is initiated sooner, but cannot begin an SDRAM cycle until the precharge-to- ACTV Freescale Semiconductor Column Column Column Column CASL read Figure 7-6 ...

Page 116

... Figure 7-7. Burst Write SDRAM Access or commands to service the transfer size with the given port size WRITE commands to assure the NOP ACTV or command. WRITE MCF5253 Reference Manual, Rev. 1 Column t RP NOP PALL commands) NOP -to-precharge delay delay ACTV command is generated to the PALL Freescale Semiconductor ...

Page 117

... A read requires WRITE data to be returned before the bus cycle can terminate. In continuous page mode, secondary accesses output the column address only. Freescale Semiconductor NOTE command. ACTV Column ...

Page 118

... Any SDRAM access initiated during the ACTV ACTV command is then generated and the delay required by REF command is generated. In this example, the next bus cycle ACTV is finished. RC MCF5253 Reference Manual, Rev NOP NOP PALL delay programmed into the active Freescale Semiconductor ...

Page 119

... SDRAM. When IS is cleared, the self-refresh operation. BCLK SDRAS SDCAS RCD SDWE SD_CS0 BCLKE (DCR[COC PALL NOP Freescale Semiconductor t RC REF NOP Figure 7-10. Auto-Refresh Operation command is sent to the DRAM controller. SELFX Self- SELF SELFX Refresh Active Figure 7-11. Self-Refresh Operation MCF5253 Reference Manual, Rev ...

Page 120

... MRS 7-16 ) before any other execution. RP command, determine if the DMR mask bits need to be modified to allow NOTE or command for each transfer within the burst, the READ WRITE NOTE MCF5253 Reference Manual, Rev PALL Freescale Semiconductor ...

Page 121

... ACTV Precharge command to Last data input to PALL Auto refresh period for 4096 rows (t Freescale Semiconductor command to that SDRAM. The address of the access should be MRS access can be a read or write. The important thing is that the address output BCLK A[31:0] ...

Page 122

... Table 7-13. SDRAM Hardware Connections A13 A12 A11 A10 A9 A17 RTIM Figure 7-13. Initialization Values for DCR Table 7-14. DCR Initialization Values Description MCF5253 Reference Manual, Rev. 1 A18 A19 A20/A24 A21 A9 A10 = CMD A11 BA0 Table 7-14. timing. ACTV Freescale Semiconductor A22 BA1 ...

Page 123

... Reserved. Don’t care. 13–12 01 Indicates a delay of data 1 cycle after CAS is asserted. CASL 11 – Reserved. Don’t care. 10–8 010 Command bit is pin 19 and bank selects are 20 and up. CBM Freescale Semiconductor SDRAM Component Bank 1 512 Kbyte 1 MB 512 Kbyte Figure 7-14. SDRAM Configuration ...

Page 124

... Reserved. Don’t care Allow reads and writes WP 7 – Reserved 7-20 Description BAM C/I – – – 0 – 0 Figure 7-16. DMR0 Register Table 7-16. DMR0 Initialization Values Description MCF5253 Reference Manual, Rev – Table 7-16. Freescale Semiconductor 16 – ...

Page 125

... MCF5253 Pins A22 A21 A20 A19 A18 A17 A9 A10 A11 A12 A13 A14 Freescale Semiconductor Description Table 7-17. Mode Register Initialization SDRAM Pins Mode Register Initialization BA1 / A13 BA0 / A12 A11 Reserved command / A10 A9 Opmode A8 Opmode ...

Page 126

... BA1 / A13 BA0 / A12 A11 Reserved – – – – – – – – 0 //Write to memory location to init. precharge MCF5253 Reference Manual, Rev. 1 – 0 – – – – – – //Initialize DCR //Initialize DACR0 //Initialize DMR0 //Set DACR0[IP] Freescale Semiconductor – ...

Page 127

... DMR0 Freescale Semiconductor //Enable refresh bit in DACR0 //Enable DACR0[IMRS]; DACR0[RE] remains set //Access SDRAM address to initialize mode register MCF5253 Reference Manual, Rev. 1 Synchronous DRAM Controller Module //Mask bit 19 of address //Set up DMR again 7-23 ...

Page 128

... Synchronous DRAM Controller Module 7-24 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 129

... MCF5253 bus signals. A brief description of the function of each signal follows. An overbar indicates an active-low signal. Signal Name A[24:1] RW D[31:16] CS0/CS4 CS1/QSPI_CS3/GPIO28 OE Freescale Semiconductor NOTE Table 8-1. MCF5253 Bus Signal Summary Direction Out Out In/Out Out Out Out MCF5253 Reference Manual, Rev ...

Page 130

... The port width for each chip-select and DRAM bank are user programmable. If none of the chip-selects, DRAM bank or System Bus Controller (SBC) spaces match the address decode, the memory cycle will 8-2 NOTE Table 8-2. Reset Port Settings 16 Bit Internal termination, 15 wait cycles MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... The OE pin on the MCF5253 will be pulled low during any read cycle from a device selected by CS0, CS1, CS2, or CS4. 8.3 Clock and Reset Signals These signals provide the external system interface for the MCF5253 (see Signal Name RSTI BCLK Freescale Semiconductor Table 8-3. Chip Select Settings Description Table 8-4. CF-Bus Signal Summary Direction In Reset In Out System Bus Clock Output (SYSCLK) MCF5253 Reference Manual, Rev ...

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... Required input hold time relative to BCLK edge hi Figure 8-1. Signal Relationship to BCLK for Non-DRAM Access 8.5 Data Transfer Operation Data transfer between the MCF5253 processor and other devices involves the following signals: 1. Address bus (A[23:1 control 8 MCF5253 Reference Manual, Rev. 1 Section 8.7, “Reset Freescale Semiconductor ...

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... When a bus cycle is initiated, the processor compares the address of that bus cycle with the base address and mask configurations programmed for various memory-mapped peripherals. These include SRAM0, SRAM1, System Bus Controller 1 and 2, chip selects, and the DRAM match is found, the cycle will Freescale Semiconductor D[31:24] D[23:16] ...

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... Chip Select Control while the read cycle timing diagram is shown in MCF5253 Reference Manual, Rev. 1 Type of Access on-chip SRAM SBC 2 SBC 1 as defined by Chip-Select control register as defined by DRAM control register Undefined Undefined Figure 8-4 Figure 8-4. Freescale Semiconductor ...

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... RW high not already high. STATE 1 The appropriate CS and OE are asserted on the falling edge of BCLK. STATE 2 Freescale Semiconductor 1. Decode address and select appropriate device 2. Drive data on D[31:16 unit asserts TA (internal termination) or assert TA externally for 1 BCLK cycle (external termination) ...

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... Chip Select Control Write cycle timing diagram is 1. Decode Address 2. Store Data on D[31:16 unit asserts TA (internal termination) or assert TA externally for 1 BCLK cycle (external termination). Figure 8-5. Write Cycle Flowchart MCF5253 Reference Manual, Rev. 1 Figure 8-7. External Memory/Device Freescale Semiconductor ...

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... For example, when a longword read is started on a word-size bus, and burst read enable is disabled into the relevant chip select register, the processor will perform two word reads back to back. Figure 8-7 shows a read, followed by a write that occurs back to back. Freescale Semiconductor ...

Page 138

... Table 8.5.5.2 Line Read Bus Cycles Figure 8-8 shows a line access read with zero wait states. 8- Read Figure 8-7. Back-to-Back Bus Cycle 8-8. Table 8-8. Allowable Line Access Patterns Addr[3:2] Longword Accesses MCF5253 Reference Manual, Rev Write Freescale Semiconductor ...

Page 139

... This figure follows the same execution as a zero-wait state read burst with the exception of an added wait state. Figure 8-9. Line Read Burst (no wait cycles) Line Write Bus Cycles Freescale Semiconductor NOTE Figure 8-8. Line Read Burst (one wait cycle) MCF5253 Reference Manual, Rev ...

Page 140

... S6). Each subsequent pipelined write data burst will be a single cycle. CS remains asserted throughout the burst transfer. 8-12 Figure 8-10. Line Read Burst-Inhibited NOTE MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 141

... For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words (opcodes) must reside on word boundaries. An address error exception will occur with any attempt to prefetch an instruction word at an odd address. Freescale Semiconductor Figure 8-13. Line Write Burst-Inhibited MCF5253 Reference Manual, Rev. 1 ...

Page 142

... OP 0 Figure 8-14. Misaligned Longword Transfer – – – Figure 8-15. Misaligned Word Transfer reaches the minimum operating specification. The crystal should start MCF5253 Reference Manual, Rev. 1 Figure 8-14 is similar to the example – – – – – – – Freescale Semiconductor ...

Page 143

... This reset helps recovery from runaway software or nonterminated bus cycles. During the software watchdog reset period all signals are driven either to a high impedance state or a negated state as appropriate. Freescale Semiconductor >16 CLKIN CYCLES Figure 8-16 ...

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... Bus Operation 8-16 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... This chapter provides the SIM register memory map, programming and configuration register descriptions, interrupt interface register descriptions, secondary interrupt controller register descriptions, and software interrupts. Freescale Semiconductor ® core and the internal peripherals or external devices. The SIM also MCF5253 Reference Manual, Rev. 1 ...

Page 146

... Reserved MPARK – Reserved – – – – – – – – – – – IPR IMR ICR0 ICR4 MCF5253 Reference Manual, Rev. 1 for more details. Description 1 2 SYPCR SWIVR SWSR Reserved ICR1 ICR2 ICR3 ICR5 ICR6 ICR7 Freescale Semiconductor 3 ...

Page 147

... MBAR2 can be read when in debug mode using background debug commands. At system reset, the MBAR valid bits (MBAR[0], MBAR2[0]) are cleared to prevent incorrect reference to resources before the MBAR or MBAR2 are written. The remainder of the MBAR and MBAR2 bits are Freescale Semiconductor Table 9-2. SIM Memory Map (continued) Description ...

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... IACK cycle not responded to by MBAR peripherals 9 – – – – – – – – – – – – Description MCF5253 Reference Manual, Rev. 1 Table 9-2 shows the bits in the Access: User read/write – – – – – C – – – – – Freescale Semiconductor – ...

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... The Base Address field defines the base address for a 1024 Mbyte address range. If V-bit in MBAR2 is set, address BA range Base Address to BaseAddress + $3FFF FFFF are mapped to MBAR2 space, and cannot be used for MBAR, SDRAM or Chip Select. 29–8 Reserved, should be cleared. Freescale Semiconductor Description ...

Page 150

... The primary interrupt controller is centralized, and services the following: • Software Watchdog Timer (SWT) • Timer modules 2 • module 9-6 Description Part Number – Figure 9-3. DeviceID Register (DeviceID) MCF5253 Reference Manual, Rev. 1 Access: User read Mask Revision – – – – – – Freescale Semiconductor ...

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... MBAR + $055 ICR9 MBAR + $056 ICR10 MBAR + $057 ICR11 Primary interrupts are programmed to a level and priority. All primary interrupts have a unique Interrupt Control Register (ICR). There are 28 possible priority levels, for the primary interrupts. Freescale Semiconductor Width Description 8 SWT 8 TIMER 0 8 ...

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... Lower 01 Low 10 High 11 Higher Table 9-8. Interrupt Priority Scheme Internal Module ICR Reg IL[2:0] IP[1] IP[0] 111 1 1 111 1 0 MCF5253 Reference Manual, Rev. 1 Access: User read/write IL[0] IP[1] IP[ Table 9-7 shows the Interrupt Source Internal Module Internal Module Freescale Semiconductor ...

Page 153

... Multiple internal modules should not be assigned to the same interrupt level and same interrupt priority when configuring the ICR registers. This can cause erratic chip behavior. Freescale Semiconductor Internal Module ICR Reg IL[2:0] IP[1] IP[0] 111 0 1 111 0 0 110 1 1 110 ...

Page 154

... The IPR makes visible the interrupt sources that have an interrupt pending. 9- – – – – – TIMER1 TIMER0 SWT Figure 9-5. Interrupt Mask Register (IMR) Description MCF5253 Reference Manual, Rev. 1 Access: User read/write QSPI DMA3 – – – – Freescale Semiconductor 16 DMA2 1 0 – ...

Page 155

... Interrupt pending registers and interrupt mask registers are decentralized, and available in the modules that own the interrupts. Table 9-11. Secondary Interrupt Controller Registers Memory Map Address MBAR2 + $140 MBAR2 + $144 MBAR2 + $148 MBAR2 + $14C MBAR2 + $150 MBAR2 + $154 MBAR2 + $158 MBAR2 + $15C Freescale Semiconductor – – – – – 12 ...

Page 156

... INT3 INT2 INT1 INT0 INT11 INT10 INT9 INT8 INT19 INT18 INT17 INT16 INT27 INT26 INT25 INT24 INT35 INT34 INT33 INT32 INT43 INT42 INT41 INT40 INT51 INT50 INT49 INT48 INT59 INT58 INT57 INT56 Access: User read/write BASE[2] BASE[1] BASE[ Freescale Semiconductor ...

Page 157

... See Table 9-15 57 See Table 9-15 56 CDROMNEWBLOCK 55 CDROMILSYNC 54 CDROMNOSYNC 53 CDROMCRCERR 52 USB 51 ATA 50 SOFTINT3 Freescale Semiconductor Description spurvec[5] spurvec[4] spurvec[3] – – – Figure 9-8. Spurvec Register Table 9-14. Secondary Interrupt Sources Module A convertor IIC1 iic1 interrupt SIM IP address error cycle interrupt ...

Page 158

... IEC958 receiver 1 bit or symbol error AUDIO Processor data in 3 under/over AUDIO U channel transmit register is empty AUDIO U channel transmit register underrun AUDIO U channel transmit register next byte will be first AUDIO IEC 958 -1 U/Q channel buffer full interrupt MCF5253 Reference Manual, Rev. 1 Description Freescale Semiconductor ...

Page 159

... INTLEVEL1FALL 3 INTLEVEL1RISE 4 SHIFTBUSY2FALL 5 SHIFTBUSY2RISE 6 INTLEVEL2FALL 7 INTLEVEL2RISE Freescale Semiconductor Module AUDIO New C-channel received on IEC958-2 AUDIO Validity flag not good on IEC958-2 AUDIO IEC958-2 receiver parity error or symbol error AUDIO IEC958-2 U/Q channel buffer full interrupt AUDIO IEC958 receiver 1U/Q channel error AUDIO ...

Page 160

... Write one to this bit to clear softint3 W Write one to this bit to clear softint2 W Write one to this bit to clear softint1 W Write one to this bit to clear softint0 MCF5253 Reference Manual, Rev. 1 Reset Associated Interrupt Interrupt Read data 58 Write data 58 Read data 57 Write data 57 Int No Note Freescale Semiconductor ...

Page 161

... For the Software Watchdog Timer Reset The last reset was caused by the software watchdog timer. If SWRI in the SYPCR is set and the software watchdog timer times out, a hardware reset occurs. 9.5.2 Software Watchdog Timer The Software Watchdog Timer (SWT) prevents system lockup if the software become trapped in loops with no controlled exit. Freescale Semiconductor SWTR 0 ...

Page 162

... SWTAVAL BIT IN THE SYPCR TO DETERMINE WHETHER OR NOT SWT TA WAS NEEDED. IF SO, EXECUTE CODE TO IDENTIFY BAD ADDRESS. NOTE: RECOMMEND THAT SWT IRQ BE SET TO THE HIGHEST LEVEL IN THE SYSTEM. 3. HELD UNTIL ANOTHER BUS CYCLE STARTS SWT TIMEOUT SWT IACK CYCLE MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... If SWT timeout occurs, SWT generates an interrupt to the core processor at the level programmed into the IL bits of ICR0. 1 SWT causes soft reset to be asserted for all modules of the part. 5 Software Watchdog Prescalar SWP 0 SWT clock not prescaled. 1 SWT clock prescaled by a value of 8192. Freescale Semiconductor SWP SWT[1] SWT[0] 0 ...

Page 164

... The SWIVR is an 8-bit supervisor write-only register. This register is set to the uninitialized vector $0F at system reset. 9-20 Description Table 9-19. SWT Timeout Period SWT[1:0] SWT TIMEOUT PERIOD BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK NOTE MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 165

... MCF5253. One is the CPU, the other is the DMA unit. Both can access internal registers within the MCF5253 peripherals. MPARK register bit encoding. The MPARK is an 8-bit read-write register. Freescale Semiconductor SWIV5 ...

Page 166

... Then when the DMA asserts its internal bus request signal, it will then have priority. 9- IARBCTRL EARBCTRL SHOWDATA Section 14.4, “DMA Memory Map and Register NOTE MCF5253 Reference Manual, Rev. 1 Access: User read/write BCR24BIT Definitions”), the Freescale Semiconductor ...

Page 167

... Current Lowest Priority Master Priority Master Core DMA DMA Core Freescale Semiconductor Default Bus Master Number Round Robin between DMA and ColdFire Core Park on master ColdFire Core Park on master DMA Module Park on current master Table 9-21. Round Robin (PARK[1:0] = 00) Next Arbitration Cycle Highest ...

Page 168

... GPIO1-EN 32 output enable 32 function select 32 interrupt status 32 interrupt clear 32 interrupt enable MCF5253 Reference Manual, Rev. 1 Definitions” for memory maps and bit Reset Value Access R 0 R/W 0 R/W 0 R/W – R/W 0 R/W 0 R/W – R – R/W Freescale Semiconductor ...

Page 169

... QSPICS0/EBUIN4/GPIO15 GPIO-READ(14) EBUIN3/CMD_SDIO2/GPIO14 GPIO-READ(13) EBUIN2/SCLKOUT/GPIO13 GPIO-READ(12) TA/GPIO12 GPIO-READ(11) MCLK1/GPIO11 GPIO-READ(10) SCL1/TXD1/GPIO10 GPIO-READ(9) none GPIO-READ(8) SDATAI3/GPIO8 GPIO-READ(7) none GPIO-READ(6) EF/RXD2/GPIO6 Freescale Semiconductor General Purpose Input GPIO1-READ(63) GPIO1-READ(62) GPIO1-READ(61) GPIO1-READ(60) GPIO1-READ(59) GPIO1-READ(58) GPIO1-READ(57) GPIO1-READ(56) GPIO1-READ(55) GPIO1-READ(54) GPIO1-READ(53) GPIO1-READ(52) GPIO1-READ(51) GPIO1-READ(50) GPIO1-READ(49) GPIO1-READ(48) GPIO1-READ(47) ...

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... The registers GPIO-INT-STAT, GPIO-INT-CLEAR and GPIO-INT-EN also control some audio interrupts. Set the GPIO_FUNCTION register bit for interrupts, as applicable. 9-26 General Purpose Input GPIO1-READ(37) GPIO1-READ(36) GPIO1-READ(35) GPIO1-READ(34) GPIO1-READ(33) GPIO1-READ(32) NOTE NOTE NOTE MCF5253 Reference Manual, Rev. 1 Read From Pin EBUOUT1/GPIO37 EBUIN1/GPIO36 SCLK3/GPIO35 SDATAO2/GPIO34 IDE_IORDY/GPIO33 IDE_DIOW/GPIO32 Freescale Semiconductor ...

Page 171

... As an example, the logic that drives pin SCLK3/GPIO35 is shown in Figure 9-15. The primary output function of the pin is the SCLK3 function it can be configured as a general-purpose output (GPIO35) by setting its controlling bit (35) in the GPIO1-FUNCTION register. Freescale Semiconductor GPIO-INT-STAT, GPIO-INT-CLEAR, GPIO-INT-EN Bit Number ...

Page 172

... I/O 52 I/O 51 I/O 50 I/O 49 MCF5253 Reference Manual, Rev. 1 SCLK3/GPIO35 Associated Pin Pin Type BCLKE/GPIO63 none none SD_CS0/GPIO60 SDRAS/GPIO59 ADOUT/SCLK4/GPIO58 none none none A23/GPO54 SDUDQM/GPO53 SDLDQM/GPO52 PSTCLK/GPIO51 PST0/GPIO50 PST1/GPIO49 Freescale Semiconductor I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O ...

Page 173

... To enable the secondary function the appropriate Pin Configuration register bit needs to be set. Note: in all cases the GPIO FUNCTION register setting has priority. Therefore it is necessary to set the appropriate GPIO FUNCTION bit enable the primary or secondary function. Freescale Semiconductor GPIO1-Function GPIO1-EN ...

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... QSPIDOUT 1 SFSY 0 SDA0 1 SDATA3 0 SCL0 1 SDATA1_BS1 14– DDATA0 0: 1 SDATA0SDIO1 1: 0 CTS1 1: 1 CTS1 0 EBUIN3 1 CMDSDIO2 0 EBUIN2 1 SCLKOUT MCF5253 Reference Manual, Rev. 1 Access: User read/write INT CTS0 RTS0 TXD1 RXD1 MON1 Description Freescale Semiconductor 17 16 INT sclk MON2 _out RXD2 TXD2 0 0 ...

Page 175

... DDATA1/RTS1/SDATA2BS2/GPIO2 M7 25 CS1/QSPICS3/GPIO28 N7 26 RCK/QSPIDIN/QSPIDOUT/GPIO26 P7 27 QSPICLK/SUBR/GPIO25 P9 28 QSPICS2/MCLK2/GPIO24 N8 29 QSPICS1/EBUOUT2/GPIO16 R7 30 QSPICS0/EBUIN4/GPIO15 F6 31 A20/A24 Freescale Semiconductor 0 PST2 1 INTMON2 0 PST3 1 INTMON1 0 SDA1 1 RXD0 0 SCL1 1 TXD0 0 DDATA3 1 RTS0 0 DDATA2 1 CTS0 24 DDATA1 0: 1 SDATA2BS2 1: 0 RTS1 1: 1 RTS1 0 CS1 1 QSPICS3 0 RCK 1 QSPIDIN / QSPIDOUT Note: QSPIDOUT is selected when CS3 is active, otherwise QSPIDIN is enabled ...

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... System Integration Module (SIM) 9-32 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 177

... GND. Depending whether a pull-up or pull-down is mounted, different options are selected as described in Table 10-1. Pin A23 Pull-up: Boot from memory connected to CS0/CS4. CS0/CS4 function is CS0 Pull-down: Boot from on-chip boot ROM. CS0/CS4 function becomes CS4 Freescale Semiconductor Table 10-1. CS0 Operation Description MCF5253 Reference Manual, Rev. 1 10-1 ...

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... BUFENB1 is always active on CS0. BUFENB2 is always inactive on CS0 programmable to be active on CS1, CS2, CS3 (special case) and CS4 as desired. 10.2.7 Bus Termination Signal – IDE_IORDY The IDE_IORDY signal controls the insertion of wait states on CS2. 10-2 for bit settings. MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

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... The MCF5253 only supports a 16-bit wide port size (PS). The size of the port controlled by a chip-select is programmable. The port size is specified by the (PS) bits in the chip select control register (CSCR). It should always be programmed as a 16-bit wide port. See for details. Freescale Semiconductor Section 10.4.2.3, “Chip Select Control Register,” MCF5253 Reference Manual, Rev. 1 Chip Select Module Section 10 ...

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... Table 10-2. Memory Map of Chip-Select Registers 1 Address Name Width MBAR + 0x80 CSAR0 16 MBAR + 0x84 CSMR0 32 10-4 for details. NOTE NOTE Description Chip-Select Address Register–Bank 0 Chip-Select Mask Register–Bank 0 MCF5253 Reference Manual, Rev Reset Access Uninitialized R/W Uninitialized R/W (except Freescale Semiconductor ...

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... Chip Select Address Register The Chip Select Address registers (CSARx) determine the base address of the corresponding chip select pin. These read/write registers are 32-bit in length. Freescale Semiconductor Description Chip-Select Control Register–Bank 0 Chip-Select Address Register–Bank 1 Chip-Select Mask Register–Bank 1 Chip-Select Control Register– ...

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... With the exception of bit 0 (V-bit), which is initialized reset, all other bits in CSMRx are uninitialized by reset. 10 – – – – – – – – – – – – Description MCF5253 Reference Manual, Rev. 1 Access: User read/write – – – – – – – – – – – – Freescale Semiconductor ...

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... The Write Protect bit can restrict write accesses to the address range in a CSAR. An attempt to write to the WP range of addresses specified in a CSAR that has this bit set results in the appropriate chip select not being selected. No exception occurs. 0 Both read and write accesses are allowed. 1 Only read access is allowed. Freescale Semiconductor ...

Page 184

... Reset – – Figure 10-3. Chip Select Control Register (CSCR0) 10-8 Description Section 10.3.3, “Global Chip-Select Figure 10 PS1 PS0 1 1 – MCF5253 Reference Manual, Rev. 1 Operation.”) and Figure 10-4. Access: User read/write BSTR BSTW – – Freescale Semiconductor 1 0 – 0 ...

Page 185

... Break data larger than the specified port size into individual non-burst writes that equals the specified port size. For example, a longword write to an 16-bit port would be broken into two individual word writes. 1 Enables burst write of data larger than the specified port size. 2–0 Reserved. Freescale Semiconductor ...

Page 186

... D0,CSAR0 move.w #$0D80,D0;CSCR0 = 3 wait states, AA=1, PS=16-bit, BEM=0, move.w D0,CSCR0 ;BSTR=0, BSTW=0 ; Program Chip Select 0 Mask Register (validate chip selects) move.l #001F0001,D0 ;Address range from $00800000 to $009FFFFF move.l D0,CSMR0;WP,EM,C/I,SC,SD,UC,UD=0; V=1 10-10 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 187

... The minimum resolution of each timer is one system clock (SYSCLK) cycle (14 MHz). The maximum timeout period (16 × 256 × 65536) ÷ 70 MHz = 3.83 seconds. ($0 - $FFFF = 65536 decimal.) 11.3 Block Diagram Figure 11 block diagram of the timer module. Freescale Semiconductor NOTE MCF5253 Reference Manual, Rev. 1 11-1 ...

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... Users can configure the timer to count until it reaches a reference value at which time it either starts a new time count immediately or continues to run. The free run/restart (FRR) bit of the TMR selects either mode. 11-2 0 TIMER CLOCK 0 GENERATOR CLOCK 0 0 MCF5253 Reference Manual, Rev. 1 SYSTEM CLOCK OR SYSTEM CLOCK/16 TOUT Freescale Semiconductor ...

Page 189

... Prescalar value = $[PS7 – PS0 7–6 These bits have no function and should be set to 00. CE Freescale Semiconductor Table 11-1 shows the timer memory map. Timer Module Registers Timer Mode Register (TMRn) Timer Reference Register (TRRn) ...

Page 190

... TCN should be incremented again. Thus, the reference register is matched after (TRR+1) time intervals. Address MBAR+$144 MBAR+$184 Reset Figure 11-3. Timer Reference Register (TRRn) 11-4 Description REFERENCE COMPARE VALUE (REF15–REF0 MCF5253 Reference Manual, Rev. 1 Access: Supervisor or User read/write Freescale Semiconductor 0 1 ...

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... If a one is read from the Output Reference Event bit, the counter has reached the TRR value. The ORI bit in the REF TMR enables the interrupt request caused by this event. Writing a one to this bit will clear the event condition. 0 Not applicable CAP Freescale Semiconductor 16-BIT TIMER COUNTER VALUE (COUNT15– ...

Page 192

... TCN to $0000. move.w #$AFAF,D0;Setup the Timer reference register (TRR0) move.w D0,TRR1 Other registers used for TIMER 0 TCR0;TIMER0 Capture Register, 16-bit, R TER0;TIMER0 Event Register, 8-bit, R/W 11-6 NOTE Bit 1 is set disable the timer MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 193

... The ADC block diagram and external circuit example is shown in the below figure. Figure 12-1. ADC Block Diagram and External Components 12.2 External Signal Description The ADC has six muxed inputs with the following pin names. 1. ADIN0/GPI52 2. ADIN1/GPI53 3. ADIN2/GPI54 Freescale Semiconductor MCF5253 Reference Manual, Rev. 1 12-1 ...

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... Source Select INTEN w1c – – MCF5253 Reference Manual, Rev. 1 Width Access Reset Value Section/Page 16 R/W Undefined 12.3.1/12 Undefined 12.3.2/12-3 Figure 12-1. ADOUT is for illustration of valid bits in the Access: User read/write ADOUT_DRIVE ADCLK_SEL – – – – Freescale Semiconductor 1 0 – – ...

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... ADvalue Register and bit fields. Address MBAR2 + 0x406 (ADVALUE Reset – – – – Freescale Semiconductor Description Figure 12-1, the ADOUT_DRIVE should be set to 00. Other circuits can use – – – – – Figure 12-3. AD Value Register (ADvalue) MCF5253 Reference Manual, Rev ...

Page 196

... To calculate the external component values use the following equation: where constant small, the ripple on the comparator input will be quite large, and there will be some mis-measurement because the average value on both comparator pins is not equal small, 12-4 Description NOTE × MCF5253 Reference Manual, Rev. 1 Eqn. 12-1 Freescale Semiconductor ...

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... When reading the same channel not necessary to ignore every other measurement. We therefore recommend to use R = 33kΩ 10nF with ADCLK = BUSCLK/256. This should produce good results for typical system clock frequencies between 30 MHz and 70 MHz. Freescale Semiconductor 1 ---------------------------------- - t ...

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... Analog to Digital Converter (ADC) 12-6 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...

Page 199

... All new IDE designs should use the ATA Interface, refer to Chapter 22, “USB, ATA DMA, and Clock Integration drive IDE designs may still be supported through this legacy IDE Interface. Freescale Semiconductor Figure 13-1 shows the bus set-up for the MCF5253 device. The figure NOTE Section 13.4, “ ...

Page 200

... Controller, etc.). The “second” bus buffer prevents the flash ROM signals from going to/from IDE and SmartMedia interfaces. The IDE and SmartMedia interfaces share most signals with the ColdFire address and data bus. 13-2 MCF5253 Reference Manual, Rev. 1 Freescale Semiconductor ...