MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 638

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

FlexCAN Module
The first write to the control/status word is important in case there was pending reception or transmission.
The write operation immediately deactivates the MB, removing it from any currently ongoing arbitration
or ID matching processes, giving time for the CPU to program the rest of the MB (see
“Message Buffer
arbitration process and eventually be transmitted according to its priority. At the end of the successful
transmission, the value of the free running timer (TIMER n ) is written into the message buffer’s time stamp
field, the code field in the control and status word is updated, a status flag is set in the IFLAG n register,
and an interrupt is generated if allowed by the corresponding IMASK n register bit. The new code field
after transmission depends on the code that was used to activate the MB in step four (see
25.6.2
The arbitration process is an algorithm executed by the message buffer management (MBM) that scans the
entire MB memory looking for the highest priority message to be transmitted. All MBs programmed as
transmit buffers will be scanned to find the lowest ID or the lowest MB number, depending on the
CANCTRL n [LBUF] bit.
The arbitration process is triggered in the following events:
Once the highest priority MB is selected, it is transferred to a temporary storage space called serial
message buffer (SMB), which has the same structure as a normal MB but is not user accessible. This
operation is called ‘move-out.’ At the first opportunity window on the CAN bus, the message on the SMB
is transmitted according to the CAN protocol rules. FlexCAN transmits up to 8 data bytes, even if the data
length code (DLC) value is bigger. Refer to
information on serial message buffers.
25.6.3
The CPU prepares or changes an MB for frame reception by writing the following:
25-22
•
•
•
•
•
1. Control/status word to hold Rx MB inactive (CODE = 0000)
2. ID word
3. Control/status word to mark the Rx MB as active and empty (CODE = 1000)
During the CRC field of the CAN frame
During the error delimiter field of the CAN frame
During intermission, if the winner MB defined in a previous arbitration was deactivated, or if there
was no MB to transmit, but the CPU wrote to the C/S word of any MB after the previous arbitration
finished
When MBM is in idle or bus off state and the CPU writes to the C/S word of any MB
Upon leaving freeze mode
Arbitration Process
Receive Process
If CANCTRL n [LBUF] is cleared, the arbitration considers not only the ID,
but also the RTR and IDE bits placed inside the ID at the same positions they
are transmitted in the CAN frame.
Deactivation”). Once the MB is activated in the fourth step, it will participate in the
MCF5253 Reference Manual, Rev. 1
Section 25.6.5.1, “Serial Message Buffers (SMBs),”
NOTE
Freescale Semiconductor
Section 25.6.5.2,
Table
25-13).
for more