MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 503

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

24.6.3.19 Endpoint Status Register (ENDPTSTATUS), Non-EHCI
This register is not defined in the EHCI specification. This register is used by the USB OTG module only
in device mode.
Freescale Semiconductor
FERB
Address MBAR2 + 0x7B8
Field
31–20 Reserved.
19–16
ERBR
15–4
ETBR
Field
15–4
3–0
3–0
Reset
Reset
W
W
R
R
Reserved.
Flush endpoint receive buffer. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed buffers.
If a packet is in progress for one of the associated endpoints, then that transfer will continue until completion. The
hardware will clear this register after the endpoint flush operation is successful.
Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is
set by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register.
There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This
delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer
ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. ETBR[3] (bit 19 of the
register) corresponds to endpoint 3.
Note: These bits will be momentarily cleared by the hardware during hardware endpoint re-priming operations when
Reserved.
Endpoint receive buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is
set by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register.
There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This
delay time varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer
ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. ERBR[3] (bit 3 of the
register) corresponds to endpoint 3.
Note: These bits will be momentarily cleared by the hardware during hardware endpoint re-priming operations when
31
15
0
0
Table 24-32. Endpoint Flush (ENDPTFLUSH) Register Field Descriptions (continued)
a dTD is retired, and the dQH is updated.
a dTD is retired, and the dQH is updated.
Table 24-33. Endpoint Status (ENDPTSTATUS) Register Field Descriptions
30
14
0
0
29
13
0
0
Figure 24-31. Endpoint Status (ENDPTSTATUS) Register
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
Description
Description
24
0
0
8
23
0
0
7
22
0
0
6
21
0
0
5
20
0
0
4
Universal Serial Bus Interface
19
0
0
3
18
Access: User read
0
0
2
ETBR
ERBR
17
0
0
1
24-41
16
0
0
0