MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 625

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
BOFFMSK
CLK_SRC
PRESDIV
ERRMSK
Offset MBAR2 0x1004 (CANCTRL0)
Reset
Reset
PSEG1
PSEG2
31–24
23–22
21–19
18–16
Field
RJW
15
14
13
W
W
R
R BOFF
MBAR2 0x2004 (CANCTRL1)
MSK
31
15
0
0
Prescaler division factor. Defines the ratio between the clock source frequency (set by CLK_SRC bit) and the serial
clock (S clock) frequency. The S clock period defines the time quantum of the CAN protocol. For the reset value,
the S clock frequency is equal to the clock source frequency. The maximum value of this register is 0xFF, that gives
a minimum S clock frequency equal to the clock source frequency divided by 256. For more information refer to
Section 25.6.8, “Bit
Resynchronization jump width. Defines the maximum number of time quanta (one time quantum is equal to the S
clock period) that a bit time can be changed by one resynchronization. The valid programmable values are 0–3.
Phase buffer segment 1. Defines the length of phase buffer segment 1 in the bit time. The valid programmable
values are 0–7.
Phase buffer segment 2. Defines the length of phase buffer segment 2 in the bit time. The valid programmable
values are 1–7.
Bus off interrupt mask.
0 Bus off interrupt disabled
1 Bus off interrupt enabled
Error interrupt mask.
0 Error interrupt disabled
1 Error interrupt enabled
Clock source. Selects the clock source for the CAN interface to be fed to the prescalar. This bit should only be
changed while the module is disabled.
0 Clock source is CRIN
1 Clock source is the internal bus clock, SYSCLK
MSK
ERR
30
14
0
0
Table 25-3. FlexCAN Control (CANCTRLn) Register Field Descriptions
CLK_
SRC
29
13
0
0
LPB
Figure 25-5. FlexCAN Control (CANCTRLn) Register
PRESDIV
28
12
Timing.”
0
0
Phase buffer segment 2
Phase buffer segment 1
Resync jump width = (RJW + 1) time quanta
27
11
0
0
MCF5253 Reference Manual, Rev. 1
S clock frequency
26
10
0
0
25
0
0
9
24
=
0
0
8
=
Description
=
(PSEG2 + 1) time quanta
(PSEG1 + 1) time quanta
SYSCLK CRIN
---------------------------------------- -
PRESDIV + 1
SMP
23
0
0
7
RJW
BOFF
REC
22
0
0
6
TSYN LBUF LOM
21
0
0
5
PSEG1
20
0
0
4
19
0
3
0
Access: User read/write
18
0
0
2
FlexCAN Module
PROPSEG
PSEG2
Eqn. 25-1
Eqn. 25-2
Eqn. 25-3
Eqn. 25-4
17
0
0
1
25-9
16
0
0
0