MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 512

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.8.3.2
DWords 1 through 8 are eight slots of transaction control and status. Each transaction description includes:
The host controller uses the information in each transaction description plus the endpoint information
contained in the first three DWords of the Buffer Page Pointer list, to execute a transaction on the USB.
24-50
31–28
27–16 Transaction n
2–1
Bit
0
Bit
15
•
•
•
Status results field
Transaction length (bytes to send for OUT transactions and bytes received for IN transactions).
Buffer offset. The PG and Transaction n Offset fields are used with the buffer pointer list to
construct the starting buffer address for the transaction.
Name
Typ
T
Length
Name
Status
ioc
iTD Transaction Status and Control List
the Host Controller to perform the proper type of processing on the item after it is fetched. Value encodings
are:
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor
11 FSTN (frame span traversal node)
Terminate
1 Link Pointer field is not valid
0 Link Pointer field is valid
This field indicates to the Host Controller whether the item referenced is an iTD, siTD or a QH. This allows
This field records the status of the transaction executed by the host controller for this slot. This field is
a bit vector with the following encoding:
31 Active. Set by the software to enable the execution of an isochronous transaction by the Host
30 Data Buffer Error. Set by the Host Controller during status update to indicate that the Host Controller
29 Babble Detected. Set by the Host Controller during status update when” babble” is detected during
28 Transaction Error (XactErr). Set by the Host Controller during status update in the case where the
For an OUT, this field is the number of data bytes the host controller will send during the transaction.
The host controller is not required to update this field to reflect the actual number of bytes transferred
during the transfer. For an IN, the initial value of the endpoint to deliver. During the status update, the
host controller writes back the field is the number of bytes the host expects the number of bytes
successfully received. The value in this register is the actual byte count (for example, 0 zero length
data, 1 one byte, 2 two bytes, etc.). The maximum value this field may contain is 0xC00 (3072).
Interrupt on complete. If this bit is set, it specifies that when this transaction completes, the Host
Controller should issue an interrupt at the next interrupt threshold.
Controller. When the transaction associated with this descriptor is completed, the Host Controller
sets this bit to zero indicating that a transaction for this element should not be executed when it is
next encountered in the schedule.
is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast
enough during transmission (underrun). If an overrun condition occurs, no action is necessary.
the transaction generated by this descriptor.
host did not receive a valid response from the device (Time-out, CRC, Bad PID, etc.). This bit may
only be set for isochronous IN transactions.
Table 24-38. Next Schedule Element Pointer (continued)
Table 24-39. iTD Transaction Status and Control
MCF5253 Reference Manual, Rev. 1
Description
Description
Freescale Semiconductor