MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 423

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

RAMADDR
22.2.2
22.2.3
22.2.4
See
Freescale Semiconductor
Offset: MBAR2 0x508 (ATA_DCOUNT)
ATAADDR
Offset: MBAR2 0x504 (ATA_DADDR)
Reset 0
Reset 0
COUNT
31–18
17–16
31–16
Field
Field
15–2
15–0
1–0
W
R
Chapter 26, “Real-Time Clock”
W
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
DMA address on the RAM side of the bus.
Reserved, should be cleared.
DMA address on the ATA side of the bus.
Reserved, should be cleared.
Reserved, should be cleared.
ATA DMA word count. Indicates amount of words to transfer on the ATA DMA bus.
0
ATA DMA Address Register (ATA_DADDR)
ATA DMA Count Register (ATA_DCOUNT)
RTC Time Register (RTC_TIME)
0
0
0
0
Table 22-3. ATA DMA Address Register (ATA_DADDR) Field Descriptions
Table 22-4. ATA DMA Count Register (ATA_DCOUNT) Field Descriptions
0
0
0
0
RAMADDR
Figure 22-2. ATA DMA Address Register (ATA_DADDR)
0
Figure 22-3. ATA DMA Count Register (ATA_DCOUNT)
0
0
0
0
0
0
0
for a detailed description of this register.
MCF5253 Reference Manual, Rev. 1
0
0
0
0
0
0
0
0
0
0
Description
Description
0
0
0
0
0
0
0
0
0
0
USB, ATA DMA, and Clock Integration Module
0
0
0
0
ATAADDR
0
9
9
0
COUNT
0
8
0
8
0
7
0
7
0
6
0
Access: User read/write
6
Access: User read/write
0
5
0
5
0
4
0
4
0
3
0
3
0
2
0
2
0
1
1
0
22-3
0
0
0
0