MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 456

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Advanced Technology Attachment Controller (ATA)
23.5.2.5.2
See
description of the bit fields.
23-30
Address MBAR2 + 0x82C (INTERRUPT_ENABLE)
controller_idle
fifo_underflow
Uncommitted
fifo_overflow
ata_intrq1
ata_intrq2
Reset
Field
Field
Figure 23-41
2–0
W
7
6
5
4
3
R
ata_intrq1
0
7
ATA interrupt request 1. This bit reflects the value of the ATA_INTRQ interrupt input. It is set in the interrupt
pending register when the drive interrupt is pending, cleared otherwise. When the bit is set in the interrupt
pending register, and the same bit is set in the interrupt enable register, fifo_txfer_end_alarm will be asserted,
signalling the DMA the end of the transfer. The interrupt clear register has no influence on this bit.
FIFO underfow. This bit reports FIFO underflow. Sticky bit. It is set in the interrupt pending register when there
is a FIFO underflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit
is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be
active, signalling interrupt to the cpu.
FIFO overflow. This bit reports FIFO overflow. Sticky bit. It is set in the interrupt pending register when there is
a FIFO overflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit is set
in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active,
signalling interrupt to the cpu.
Controller Idle. This bit reports controller idle. It is set when the ATA protocol engine is idle, there is no activity
on the ATA bus. It is cleared when there is activity on the ATA bus. When the bit is set in the interrupt pending
register, and the same bit is set in the interrupt enable register, ipbus_int will be active, signalling interrupt to the
cpu. The interrupt clear register has no influence on this bit.
ATA interrupt request 2. This bit reflects the value of the ATA_INTRQ interrupt input. It is set in the interrupt
pending register when the drive interrupt is pending, cleared otherwise. It has exactly same functioning as
ata_intrq1, but this bit affects ipbus_int, while the other affects interrupt to the DMA. When the bit is set in the
interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be asserted,
signalling the CPU the drive is requesting attention. The interrupt clear register has no influence on this bit.
N/A
Interrupt_Enable Register
for illustration of valid bits in the Interrupt_Enable Register and
Table 23-11. Interrupt Pending Register Field Description (continued)
fifo_underflow
0
6
Table 23-12. Interrupt Enable Register Field Description
Figure 23-41. Interrupt_Enable Register
fifo_overflow
MCF5253 Reference Manual, Rev. 1
0
5
controller_idle
0
4
Description
Description
ata_irtrq2
0
3
–
2
Table 23-12
Freescale Semiconductor
Access: User read/write
–
1
for
0
–