MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 135

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

A basic read bus cycle has six states (S0–S5). The signal timing relationship in the constituent states of a
basic read cycle is as follows:
Freescale Semiconductor
STATE 0
STATE 1
STATE 2
Name
State
D[31:16]
A[23:1]
BCLK
1. Sample TA low and latch data
1. Start next cycle
1. Set RW to read
2. Place address on A[23:1]
CSx
RW
OE
TA
The read cycle is initiated in state 0 (S0). On the rising edge of BCLK, the MCF5253 places a valid address on
the address bus and drives RW high, if it is not already high.
The appropriate CS and OE are asserted on the falling edge of BCLK.
MCF5253
S0
Figure 8-4. Basic Read Bus Cycle
Figure 8-3. Read Cycle Flowchart
MCF5253 Reference Manual, Rev. 1
Table 8-6. Read Cycle States
S1
S2
Description
S3
Read
1. Stop Driving D[31:16]
1. Decode address and select appropriate device
2. Drive data on D[31:16]
3. CS unit asserts TA (internal termination)
or assert TA externally for 1 BCLK cycle (external
termination).
1,2
S4
External Memory/Device
S5
Bus Operation
8-7