MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 431

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

23.4.1.2
This signal correspond to ATA signal DIOR. During PIO and multiword DMA transfer, function is read
strobe. During ultra DMA in burst, function is HDMARDY. During ultra DMA out burst, function is host
strobe.
23.4.1.3
This signal corresponds to ATA signal DIOW. During PIO and multiword DMA transfer, function is write
strobe. During ultra DMA burst, function is STOP, signalling whenever host wants to terminate running
ultra DMA transfer.
23.4.1.4
These signals are the address group of the ATA bus. ATA_CS0 and ATA_CS1 are the chip selects;
ATA_A0, ATA_A1, and ATA_A2 are the 3 address lines. All five lines follow the same timing.
23.4.1.5
This signal is the ATA bus device DMA request. It is pulled high by the device if it wants to transfer data
using multiword DMA or ultra DMA mode.
23.4.1.6
This signal is the ATA bus host DMA acknowledge. It is pulled low by the host when it grants the DMA
request.
23.4.1.7
This signal is the ATA bus interrupt request. It is pulled high by the device whenever it wants to interrupt
the host CPU.
23.4.1.8
This signal is the ATA bus IORDY line. It has three functions:
23.4.1.9
This is the ATA data bus.
23.4.2
To meet electrical spec on the ATA bus, several requirements must be met. For a detailed description, refer
to the ATA specification.
Freescale Semiconductor
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IORDY⎯active low wait during PIO cycles
DDMARDY⎯active low device ready during ultra DMA out transfers
DSTROBE⎯device strobe during ultra DMA in transfers
Electrical Spec on the ATA Bus, Bus Buffers
ATA_DIOR (Out)
ATA_DIOW (Out)
ATA_CS0, ATA_CS1, ATA_A0, ATA_A1, ATA_A2 (Out)
ATA_DMARQ (In)
ATA_DMACK (Out)
ATA_INTRQ (In)
ATA_IORDY (In)
ATA_D[15:0] (In/Out/Tri-state)
MCF5253 Reference Manual, Rev. 1
Advanced Technology Attachment Controller (ATA)
23-5