MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 65

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

3.2.1.2
Registers A0–A6 can be used as software stack pointers, index registers, or base address registers as well
as for word and longword operations.
3.2.1.3
The ColdFire architecture supports a single hardware stack pointer (A7) for explicit references as well as
for implicit ones during stacking for subroutine calls and returns and exception handling. The initial value
of A7 is loaded from the reset exception vector, address $0. The same register is used for both user and
supervisor mode as well as word and longword operations.
A subroutine call saves the Program Counter (PC) on the stack and the return restores it from the stack.
Both the PC and the Status Register (SR) are saved to the stack during the processing of exceptions and
interrupts. The return from exception instruction restores the SR and PC values from the stack.
3.2.1.4
The PC contains the address of the next instruction to execute. During instruction execution and exception
processing, the processor automatically increments the contents of the PC or places a new value in the PC,
as appropriate. For some addressing modes, the PC can be used as a pointer for PC-relative operand
addressing.
3.2.1.5
The CCR is the least significant byte of the processor status register (SR). Refer to Status Register (SR)
on
results generated by processor operations. Bit 4, the extend bit (X bit), is also used as an input operand
during multiprecision arithmetic computations.
Table 3-2
Freescale Semiconductor
Field
7–5
Section 3.5, “Processor
4
3
2
Code
describes the bits in the condition code register.
N
X
Z
–
Address Registers (A0–A6)
Stack Pointer (A7, SP)
Program Counter (PC)
Condition Code Register (CCR)
Reserved, should be cleared.
Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not
affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic.
Negative condition code bit. Set if the msb of the result is set; otherwise cleared.
Zero condition code bit. Set if the result equals zero; otherwise cleared.
Exceptions” for more information. Bits 4–0 represent indicator flags based on
7
–
Table 3-1. Condition Code Register (Bits 0–4)
Table 3-2. CCR Register Field Description
6
–
MCF5253 Reference Manual, Rev. 1
5
–
X
4
N
3
Description
2
Z
V
1
C
0
ColdFire Core
3-3