MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 517

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

24.8.4.4
DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page
cross. The most significant 20 bits of each DWord in this section are the 4K (page) aligned buffer pointers.
The least significant 12 bits of each DWord are used as additional transfer state.
Freescale Semiconductor
31–12
11–0
7–0
Bit
Bit
Current Offset
Buffer Pointer
(Page 0)
Name
Status
Name
siTD Buffer Pointer List (Plus)
This field records the status of the transaction executed by the host controller for this slot. This field
is a bit vector with the following encoding:
The 12 least significant bits of the Page 0 pointer is the current byte offset for the current page
Bits [31–12] is a 4K page-aligned, physical memory addresses. These bits correspond to physical
address bits [31–12] respectively. The field P specifies the current active pointer
pointer (as selected with the page indicator bit (P field)). The host controller is not required to write
this field back when the siTD is retired (Active bit transitioned from a one to a zero).
Table 24-47. siTD Transfer Status and Control (continued)
Status Bit
7
6
5
4
3
2
1
0
Table 24-48. siTD Buffer Pointer Page 0 (Plus)
Active. Set by the software to enable the execution of an isochronous split
transaction by the Host Controller.
ERR. Set by the Host Controller when an ERR response is received from the
Companion Controller.
Data Buffer Error. Set by the Host Controller during status update to indicate that the
Host Controller is unable to keep up with the reception of incoming data (overrun) or
is unable to supply data fast enough during transmission (under run). In the case of
an under run, the Host Controller will transmit an incorrect CRC (thus invalidating the
data at the endpoint). If an overrun condition occurs, no action is necessary.
Babble Detected. Set by the Host Controller during status update when” babble” is
detected during the transaction generated by this descriptor.
Transaction Error (XactErr). Set by the Host Controller during status update in the
case where the host did not receive a valid response from the device (Time-out,
CRC, Bad PID, etc.). This bit will only be set for IN transactions.
Missed Micro-Frame. The host controller detected that a host-induced hold- off
caused the host controller to miss a required complete-split transaction.
Split Transaction State (SplitXstate). The bit encodings are:
0 Do Start Split. This value directs the host controller to issue a Start split
1 Do Complete Split. This value directs the host controller to issue a Complete split
Reserved. Bit reserved for future use and should be cleared.
MCF5253 Reference Manual, Rev. 1
transaction to the endpoint when a match is encountered in the S-mask.
transaction to the endpoint when a match is encountered in the C-mask.
Description
Description
Definition
Universal Serial Bus Interface
24-55