MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 506

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.6.3.22 Endpoint Control Register n (ENDPTCTRLn), Non-EHCI
These registers are not defined in the EHCI specification. There is an ENDPTCTRLn register of each
endpoint in a device.
24-44
Address MBAR2 + 0x7C4 (ENDPTCTRL1)
31–24
19–18
Field
TXE
TXR
TXT
TXD
Reset
Reset
TXI
23
22
21
20
17
W
W
R
R
MBAR2 + 0x7C8 (ENDPTCTRL2)
MBAR2 + 0x7CC (ENDPTCTRL3)
Reserved.
TX endpoint enable.
1 Enabled
0 Disabled
TX data toggle reset. Whenever a configuration event is received for this Endpoint, the software must write a one to
this bit in order to synchronize the data PID’s between the Host and device.
TX data toggle inhibit. This bit is used for test only and should always be written as zero. Writing a one to this bit will
cause this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
1 PID Sequencing Disabled
0 PID Sequencing Enabled
Reserved.
TX endpoint type.
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should be
configured as a bulk type endpoint.
TX endpoint data source. This bit should always be written as 0, which selects the Dual Port Memory/DMA Engine
as the source.
31
15
0
0
Table 24-36. Endpoint Control 1 to 3 (ENDPTCTRLn) Register Field Descriptions
30
14
0
0
29
13
Figure 24-34. Endpoint Control 1 to 3(ENDPTCTRLn) Register
0
0
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
Description
24
0
0
8
RXE
TXE
23
0
0
7
RXR
TXR
22
0
0
6
RXI
TXI
21
0
0
5
20
0
0
4
19
0
0
3
Freescale Semiconductor
Access: User read/write
RXT
TXT
18
0
0
2
RXD
TXD
17
0
0
1
RXS
TXS
16
0
0
0