MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 95

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Bit Name
DBWE
23–11
CLNF
CINV
CEIB
DCM
DWP
5–2
1–0
24
10
9
8
7
6
The Cache Invalidate bit forces the cache to invalidate each tag array entry. The invalidation process requires 32
machine cycles, with a single cache entry cleared per machine cycle. The state of this bit is always read as a zero.
After a hardware reset, the cache must be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
Reserved, should be cleared.
The Cache Enable Noncacheable Instruction Bursting bit enables the line-fill buffer to be loaded with burst transfers
under control of CLINF[1:0] for non-cacheable accesses. Noncacheable accesses are never written into the memory
array.
0 Disable burst fetches on noncacheable accesses
1 Enable burst fetches on noncacheable accesses
The Default Cache Mode bit defines the default cache mode: 0 is cacheable, 1 is noncacheable. For more
information on the selection of the effective memory attributes, see
0 Default cacheable
1 Default noncacheable
The Default Buffered Write Enable bit defines the default value for enabling buffered writes. If DBWE = 0, the
termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is
completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and the operation buffered in
the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus
and the external bus.
Generally, enabled buffered writes provide higher system performance but recovery from access errors can be more
difficult. For the ColdFire CPU, reporting access errors on operand writes is always imprecise and enabling buffered
writes simply further decouples the write instruction from the signaling of the fault.
0 Disable buffered writes
1 Enable buffered writes
Reserved, should be cleared.
Default Write Protection
0 Read and write accesses permitted
1 Only read accesses permitted
Reserved, should be cleared.
The Cache Line Fill bits control the size of the memory request the cache issues to the bus controller for different
initial line access offsets.
CLNF[1:0]
Table 5-4. Cache Control Register Field Descriptions (continued)
Table 5-5. External Fetch Size Based on Miss Address and CLNF
00
01
10
11
Table 5-5
MCF5253 Reference Manual, Rev. 1
Line
Line
Line
Line
00
shows the fetch size.
Longword Address Bits
Description
Line
Line
Line
Line
01
Longword
Section 5.4.2, “Memory Reference Attributes.”
Line
Line
Line
10
Longword
Longword
Line
Line
11
Instruction Cache
5-7