MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 612

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.12.1.5 Operational Model
The operational models are well defined for the behavior of the Transaction Translator (see USB 2.0
specification) and for the EHCI controller moving packets between system memory and a USB-HS hub.
Since the embedded Transaction Translator exists within the USB module there is no physical bus between
EHCI host controller driver and the USB FS/LS bus. These sections will briefly discuss the operational
model for how the EHCI and Transaction Translator operational models are combined without the physical
bus between. The following sections assume the reader is familiar with both the EHCI and USB 2.0
Transaction Translator operational models.
24.12.1.5.1 Microframe Pipeline
The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between
the Host (H) and the Bus (B). The embedded Transaction Translator shall use the same pipeline algorithms
specified in the USB 2.0 specification for a Hub-based Transaction Translator.
All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers
are complete. As an example of the microframe pipeline implemented in the embedded Transaction
Translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be ready to execute
on the bus in B-frame 0.
It is important to note that when programming the S-mask and C-masks in the EHCI data structures to
schedule periodic transfers for the embedded Transaction Translator, the EHCI host controller driver must
follow the same rules specified in EHCI for programming the S-mask and C-mask for downstream
Hub-based Transaction Translators.
Once periodic transfers are exhausted, any stored asynchronous transfer will be moved. Asynchronous
transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to
H-frame and B-frame boundaries with the exception that an asynchronous transfer can not babble through
the SOF (start of B-frame 0).
24.12.1.5.2 Split State Machines
The start and complete split operational model differs from EHCI slightly because there is no bus medium
between the EHCI controller and the embedded Transaction Translator. Where a start or complete-split
operation would occur by requesting the split to the HS hub, the start/complete split operation is simple an
internal operation to the embedded Transaction Translator.
handshakes are emulated from internal state instead of actual handshakes to HS split bus traffic.
24-150
•
All FS ISO transactions:
— Hub Address = 0
— siTD.EPS = 00 (full speed)
Maximum Packet Size must less than or equal to 1023 or undefined behavior may result.
MCF5253 Reference Manual, Rev. 1
Table 24-94
summarizes the conditions where
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