MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 194

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Analog to Digital Converter (ADC)
The ADOUT signal on the ADOUT/SCLK4/GPIO58 pin provides the ADC comparators (ramping)
reference voltage in PWM format. This output requires an external integrator circuit (resistor/capacitor) to
convert the PWM source to a DC level which is then input to the ADREF pin. A circuit example is shown
in
Only one ADC input can be converted at any one time. The input to be converted is selected via the source
select bits of the ADconfig register. An interrupt can be provided when the ADC measurement cycle is
complete.
12.3
This section discusses the two user-accessible ADC registers, ADconfig and ADvalue.
12.3.1
The device will select one of the six inputs using multiplexer (7) as shown in
calculated via flip-flop (8) and buffer (9). The feed-back loop (1-7-8-9) will keep the voltage on the
external integrator capacitor close to ADIN0, and in this way, the voltage on ADIN0 is proportional to the
duty cycle of the signal on ADOUT.
The circuit will measure the duty cycle of the ADOUT signal. Every time ADOUT is high, counter (10)
will increment. Every 4096 AD_CLK clock pulses the value from counter (10) is latched into register (11),
and ADInterrupt is generated. Counter (10) is also reset.
On reception of ADInterrupt, the processor will read ADvalue(12:0) from the ADvalue register. This value
is in range 0-4096, and indicates duty cycle of ADOUT. See
ADconfig register and
12-2
Address MBAR2 + 0x402 (ADCONFIG)
MBAR2
Offset
Reset
Figure
0x402
0x406
4. ADIN3/GPI55
5. ADIN4/GPI56
6. ADIN5/GPI57
W
R
15
–
12-1.
ADC Memory Map and Register Definitions
ADconfig—AD configuration register
ADvalue—AD value register
AD Configuration Register (ADconfig)
14
–
13
–
12
–
Table 12-2
11
–
Figure 12-2. AD Configuration Register (ADconfig)
Source Select
10
0
Register
for description of the bit fields.
MCF5253 Reference Manual, Rev. 1
0
Table 12-1. ADC Memory Map
9
0
8
INTCLR
w1c
–
7
INTEN
–
6
Figure 12-2
Width
ADOUT_DRIVE
16
16
–
5
Access Reset Value
for illustration of valid bits in the
R/W
R
–
4
Figure
Undefined
Undefined
3
–
Freescale Semiconductor
12-1. ADOUT is
Access: User read/write
ADCLK_SEL
–
2
Section/Page
12.3.1/12-2
12.3.2/12-3
1
–
–
0