MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 401

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

ADDRESS[31:0]–High Address
This field contains the 32-bit address which marks the upper bound of the address breakpoint range.
20.5.2
The AATR defines the address attributes and a mask to be matched in the trigger. The AATR value is
compared with the address attribute signals from the processor’s local high-speed bus, as defined by the
setting of the TDR. The AATR is accessible in supervisor mode as debug control register $6 using the
WDEBUG instruction and through the BDM port using the WDMREG command. The lower five bits of
the AATR are also used for BDM command definition to define the address space for memory references
as described in
Freescale Semiconductor
Reset
Reset
Reset
14–13
12–11
Field
10–8
TMM
SZM
W
TTM
W
W
R
RM
R
R
15
R
7
RM
15
31
15
0
–
–
Address Attribute Trigger Register
Section 20.4.1.2, “Debug Module Hardware.”
14
The Read/Write Mask field corresponds to the R-field. Setting this bit causes R to be ignored in address
comparisons.
The Size Mask field corresponds to the SZ field. Setting a bit in this field causes the corresponding bit in SZ
to be ignored in address comparisons.
The Transfer Type Mask field corresponds to the TT field. Setting a bit in this field causes the corresponding
bit in TT to be ignored in address comparisons.
The Transfer Modifier Mask field corresponds to the TM field. Setting a bit in this field causes the
corresponding bit in TM to be ignored in address comparisons.
The Read/Write field is compared with the R/W signal of the processor’s local bus.
30
14
0
–
–
SZM
Table 20-19. Address Attribute Trigger Register Field Descriptions
13
29
13
0
–
–
Figure 20-30. Address Breakpoint High Register (ABHR)
Figure 20-31. Address Attribute Trigger Register (AATR)
12
28
12
0
–
–
TTM
11
27
11
0
–
–
MCF5253 Reference Manual, Rev. 1
10
26
10
0
–
–
TMM
25
0
–
–
9
9
ADDRESS[31:0]
ADDRESS[31:0]
24
0
–
–
8
8
Description
23
R
0
–
–
7
7
22
0
–
–
6
6
SZ
21
0
–
–
5
5
Background Debug Mode (BDM) Interface
20
–
–
4
0
4
TT
19
–
–
0
3
3
Access: User write only
Access: User write only
18
1
–
2
–
2
TM
17
0
–
–
1
1
20-31
16
1
–
–
0
0