MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 130

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Bus Operation
8.2.1
The address bus A[24:1] provides the address of the byte or most significant byte of the word or longword
being transferred.The address lines also serve as the SDRAM address pins, providing multiplexed row and
column address signals.
A0 is not available on the address bus. As a result, the MCF5253 supports only 16-bit port size.
8.2.2
The read/write (RW) control line will indicate that a bus cycle in progress is read or write. RW timing is
same as address timing.
8.2.3
This active-low synchronous input signal indicates the successful completion of a requested data transfer
operation. During MCF5253-initiated transfers, transfer acknowledge (TA) is an asynchronous input
signal from the referenced slave device indicating completion of the transfer.
The MCF5253 edge-detects and re-times the TA input. This means that an additional wait state may or
may not be inserted. For example, if the active chip select is used to immediately generate the TA input,
one or two wait states may be inserted in the bus access.
The TA signal function is not available after reset. It must be enabled by configuring the appropriate pin
configuration register bit (it is multiplexed with GPIO12) along with the value of CSCRn[WS]. If TA is
not used, it should either have a pull-up resistor or be driven through gating logic that always ensures the
input is inactive. TA should be negated on the negating edge of the active chip select.
TA must always be negated before it can be recognized as asserted again. If held asserted into the following
bus cycle, it has no effect and does not terminate the bus cycle.
TA is not used for termination during SDRAM accesses.
8.2.4
The data bus D[31:16] is a bidirectional, non-multiplexed bus. Data is latched by the MCF5253 on the
rising BCLK clock edge. When interfacing with external memory or peripherals, the data bus port width,
wait states, and internal termination are initially defined.
The port width for each chip-select and DRAM bank are user programmable. If none of the chip-selects,
DRAM bank or System Bus Controller (SBC) spaces match the address decode, the memory cycle will
8-2
Address Bus
Read/Write Control
Transfer Acknowledge (TA)
Data Bus
For SDRAM access A24 is multiplexed with A20.
Reset cycle length
Reset Port Size
MCF5253 Reference Manual, Rev. 1
Table 8-2. Reset Port Settings
Internal termination, 15 wait cycles
NOTE
16 Bit
Freescale Semiconductor