MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 125

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

7.6.5
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on
A[9:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding MCF5253 address pins
must be determined while being aware of masking requirements.
Table 7-17
Freescale Semiconductor
Bits
AM
SC
SD
UC
UD
C/I
6
5
4
3
2
1
0
V
Setting
1
1
1
0
1
0
1
lists the desired initialization setting:
MCF5253 Pins
Mode Register Initialization
Disable CPU space access
Disable alternate master access
Disable supervisor code accesses
Enable supervisor data accesses
Disable user code accesses
Enable user data accesses
Enable accesses
A22
A21
A20
A19
A18
A17
A10
A11
A12
A13
A14
A9
Table 7-16. DMR0 Initialization Values (continued)
Table 7-17. Mode Register Initialization
command / A10
SDRAM Pins
BA1 / A13
BA0 / A12
MCF5253 Reference Manual, Rev. 1
A11
A9
A8
A7
A6
A5
A4
A3
A2
Description
Mode Register Initialization
Reserved
Opmode
Opmode
CASL
CASL
CASL
WB
BT
BL
–
–
–
Synchronous DRAM Controller Module
0
0
0
0
0
0
–
0
0
1
0
0
7-21