MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 502

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
24.6.3.18 Endpoint Flush Register (ENDPTFLUSH), Non-EHCI
This register is not defined in the EHCI specification. This register is used by the USB OTG module only
in device mode.
24-40
Address MBAR2 + 0x7B4
31–20 Reserved.
19–16
FETB
Field
31–20
19–16
PERB
PETB
Field
15–4
3–0
Reset
Reset
W
W
R
R
Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to clear any
primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. The hardware will clear this register after the endpoint flush operation is successful.
Reserved.
Prime endpoint transmit buffer. For each endpoint, a corresponding bit is used to request that a buffer prepared for a
transmit operation in order to respond to a USB IN/INTERRUPT transaction. The software should write a one to the
corresponding bit when posting a new transfer descriptor to an endpoint. The hardware will automatically use this bit
to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. The hardware will
clear this bit when the associated endpoint(s) is (are) successfully primed. PETB[3] (bit 19 of the register) corresponds
to endpoint 3.
Note: These bits will be momentarily set by the hardware during hardware re-priming operations when a dTD is
Reserved.
Prime endpoint receive buffer. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive
operation in order to respond to a USB OUT transaction. The software should write a one to the corresponding bit
whenever posting a new transfer descriptor to an endpoint. The hardware will automatically use this bit to begin
parsing for a new transfer descriptor from the queue head and prepare a receive buffer. The hardware will clear this
bit when the associated endpoint(s) is (are) successfully primed.
Note: These bits will be momentarily set by the hardware during hardware re-priming operations when a dTD is
31
15
0
0
retired, and the dQH is updated.
retired, and the dQH is updated.
Table 24-31. Endpoint Initialization (ENDPTPRIME) Register Field Descriptions
30
14
0
0
Table 24-32. Endpoint Flush (ENDPTFLUSH) Register Field Descriptions
29
13
0
0
Figure 24-30. Endpoint Flush (ENDPTFLUSH) Register
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
Description
Description
24
0
0
8
23
0
0
7
22
0
0
6
21
0
0
5
20
0
4
0
19
0
0
3
Freescale Semiconductor
Access: User read/write
18
0
0
2
FERB
FETB
17
0
0
1
16
0
0
0