MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 310

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Audio Interface Module (AIM)
The source of the transmit data is programmable.
17.5.2
There are a number of interrupts defined for use with the serial audio transmitters:
The action of the IIS transmitters on FIFO underrun is to repeat the last sample.
Timing diagrams for IIS/EIAJ mode are shown in
output is clocked on the falling edge of the SCLK bit clock (noninverted).
17.5.3
Each of the two IIS receivers operate independently. For timing diagrams, see
Figure
SCLK/LRCK. Data is always clocked on the rising edge of the SCLK bit clock (non-inverted).
17-12
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•
•
•
•
•
•
•
•
LRCK(Sony-16 bit)
17-6. The data can be clocked into each receiver using an external or internally-generated
One of the two I
The digital audio (EBU) receiver.
Digital zero.
Serial audio interface1 transmit FIFO overrun or underrun
Serial audio interface1 transmit FIFO left/right resynchronization
Serial audio interface1 transmit FIFO empty
Serial audio interface 2 transmit FIFO overrun or underrun
Serial audio interface 2 transmit FIFO left/right resynchronization
Serial audio interface 2 transmit FIFO empty
SCLK
(inverted clock)
SCLK
(noninverted)
LRCK(IIS)
IIS/EIAJ Transmitter Interrupts
IIS/EIAJ Receiver Descriptions
Data out
Data In
Figure 17-5. IIS/EIAJ Timing Diagram (16 SCLK edges per word)
2
S receivers.
D4
D19 D18 D17
MCF5253 Reference Manual, Rev. 1
D16
Left (if noninverted)
Left (if noninverted)
D15
D14
D13
D12
Figure 17-5
D11
D10
D9
D8
D7
and
D6
D5
Figure
D4
D19
17-6. Data and word clock
D18
D17
Figure 17-5
Freescale Semiconductor
and