MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 620

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

FlexCAN Module
Once entry into freeze mode is requested, the FlexCAN waits until an intermission or idle condition exists
on the CAN bus, or until the FlexCAN enters the error passive or bus off state. Once one of these
conditions exists, the FlexCAN waits for the completion of all internal activity such as arbitration,
matching, move-in, and move-out. When this happens, the following events occur:
After engaging one of the mechanisms to place the FlexCAN in freeze mode, the user must wait for the
FRZACK bit to be set before accessing any other registers in the FlexCAN; otherwise, unpredictable
operation may occur. In freeze mode, all memory mapped registers are accessible.
To exit freeze mode, the BKPT line must be negated or the HALT bit in CANMCR n must be cleared. Once
freeze mode is exited, the FlexCAN will resynchronize with the CAN bus by waiting for 11 consecutive
recessive bits before beginning to participate in CAN bus communication.
25.3.2.3
This mode disables the FlexCAN module; it is entered by setting CANMCR n [MDIS]. If the module is
disabled during freeze mode, it shuts down the system clocks, sets the LPMACK bit, and clears the
FRZACK bit.
If the module is disabled during transmission or reception, FlexCAN does the following:
The bus interface unit continues to operate, enabling the CPU to access memory-mapped registers, except
the free-running timer, the error counter register, and the message buffers, which cannot be accessed when
the module is disabled. Exiting from this mode is done by negating the MDIS bit, which will resume the
clocks and negate the LPMACK bit.
25.3.2.4
The module enters this mode when the LPB bit in the control register is set. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream output of the
transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN
output goes to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting and
treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN
25-4
•
•
•
•
•
•
•
•
•
The FlexCAN stops transmitting/receiving frames.
The prescaler is disabled, thus halting all CAN bus communication.
The FlexCAN ignores its Rx pins and drives its Tx pins as recessive.
The FlexCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits in
CANMCR n are set.
The CPU is allowed to read and write the error counter registers (in other modes they are
read-only).
Waits to be in either idle or bus-off state, or else waits for the third bit of intermission and then
checks it to be recessive
Waits for all internal activities such as arbitration, matching, move-in, and move-out to finish
Ignores its Rx input pin and drives its Tx pin as recessive
Shuts down the system clocks
Module Disabled Mode
Loop-back Mode
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor