MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 538

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
packet size, etc.). It also uses the Page Select (PG) field to index the buffer pointer array, storing the
selected buffer pointer and the next sequential buffer pointer. For example, if PG field is a 0, then the host
controller will store Page 0 and Page 1.
The host controller constructs a physical data buffer address by concatenating the current buffer pointer
(as selected using the current transaction description's PG field) and the transaction description's
Transaction Offset field. The host controller uses the endpoint addressing information and I/O-bit to
execute a transaction to the appropriate endpoint. When the transaction is complete, the host controller
clears the active bit and writes back any additional status information to the Status field in the currently
selected transaction description.
The data buffer associated with the iTD must be virtually contiguous memory. Seven page pointers are
provided to support eight high-bandwidth transactions regardless of the starting packet’s offset alignment
into the first page. A starting buffer pointer (physical memory address) is constructed by concatenating the
page pointer (example: page 0 pointer) selected by the active transaction descriptions’ PG (example value:
0b00) field with the transaction offset field. As the transaction moves data, the host controller must detect
when an increment of the current buffer pointer will cross a page boundary. When this occurs the host
controller simply replaces the current buffer pointer’s page portion with the next page pointer (example:
page 1 pointer) and continues to move data. The size of each bus transaction is determined by the value in
the Maximum Packet Size field. An iTD supports high-bandwidth pipes via the Mult (multiplier) field.
When the Mult field is 1, 2, or 3, the host controller executes the specified number of Maximum Packet
sized bus transactions for the endpoint in the current micro-frame. In other words, the Mult field represents
a transaction count for the endpoint in the current micro-frame. If the Mult field is zero, the operation of
the host controller is undefined. The transfer description is used to service all transactions indicated by the
Mult field.
For OUT transfers, the value of the Transaction n Length field represents the total bytes to be sent during
the micro-frame. The Mult field must be set by the software to be consistent with Transaction n Length
and Maximum Packet Size. The host controller will send the bytes in Maximum Packet Size'd portions.
After each transaction, the host controller decrements it's local copy of Transaction n Length by Maximum
Packet Size. The number of bytes the host controller sends is always Maximum Packet Size or Transaction
n Length, whichever is less. The host controller advances the transfer state in the transfer description,
updates the appropriate record in the iTD and moves to the next schedule data structure. The maximum
sized transaction supported is 3 × 1024 bytes.
For IN transfers, the host controller issues Mult transactions. It is assumed that the software has properly
initialized the iTD to accommodate all of the possible data. During each IN transaction, the host controller
must use Maximum Packet Size to detect packet babble errors. The host controller keeps the sum of bytes
received in the Transaction n Length field. After all transactions for the endpoint have completed for the
micro-frame, Transaction n Length contains the total bytes received. If the final value of Transaction n
Length is less than the value of Maximum Packet Size, then less data than was allowed for was received
from the associated endpoint. This short packet condition does not set the USBINT bit in the USBSTS
register. The host controller will not detect this condition. If the device sends more than Transaction n
Length or Maximum Packet Size bytes (whichever is less), then the host controller will set the Babble
Detected bit and clear the Active bit. Note, that the host controller is not required to update the iTD field
Transaction n Length in this error scenario. If the Mult field is greater than one, then the host controller
MCF5253 Reference Manual, Rev. 1
24-76
Freescale Semiconductor