MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 421

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Chapter 22
USB, ATA DMA, and Clock Integration Module
This chapter includes the memory map, register descriptions and functional description of the ATA DMA
integration module.
22.1
This chapter includes registers that are used to configure the various modules that are new to the MCF5253
family. It also includes a shared 16 kB local memory for the ATA and USB modules.
22.2
Table 22-1
22.2.1
Freescale Semiconductor
Offset: MBAR2 0x500 (MISCCR)
Reset
Reset
MBAR2
Offset
0x50C
0x500
0x504
0x508
0x510
W
W
R
R
31
15
0
0
Introduction
Memory Map and Register Definitions
Miscellaneous Configuration Register (MISCCR)
ATA DMA Source and Destination Address Register (ATA_DADDR)
ATA DMA Count Register (ATA_DCOUNT)
RTC Time Register (RTC_TIME)
USB/FlexCAN Clock Gating (USBCANCLK)
provides the memory map and register definitions for the ATA DMA integration module.
Miscellaneous Configuration Register (MISCCR)
30
14
0
0
URIP
29
13
0
0
Figure 22-1. Miscellaneous Configuration Register (MISCCR)
URIC
28
12
0
0
0
URIE
Table 22-1. Real Time Clock Memory Map
27
11
0
0
Register
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
RTCPL RTC
24
0
0
8
CLR
23
0
0
7
DMA
END
22
0
0
6
Access Reset Value
CPU
END
R/W
R/W
R/W
R/W
21
0
0
5
R
ADIP
20
0x0000_0000
0x0000_0000
0x0000_0000
0
0
4
Undefined
Undefined
ADIC
19
0
0
3
Access: User read/write
ADIE ADTD ADTA
18
0
0
2
Section/Page
22.2.1/22-1
22.2.2/22-3
22.2.3/22-3
26.3.2/26-2
22.2.5/22-4
17
0
0
1
22-1
16
0
0
0