MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 72

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
when the access error was signaled. All programming model updates associated with the write instruction
are completed. The NOP instruction can collect access errors for writes. This instruction delays its
execution until all previous operations, including all pending write operations, are complete. If any
previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
3.5.2
Any attempted execution transferring control to an odd instruction address (i.e., if bit 0 of the target
address is set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed effective
addressing mode generates an address error as does an attempted execution of a full-format indexed
addressing mode.
3.5.3
The MCF5253 processors decode the full 16-bit opcode and generate this exception if execution of an
unsupported instruction is attempted. Additionally, attempting to execute an illegal line A or line F opcode
generates unique exception types: vectors 10 and 11, respectively.
ColdFire processors do not provide illegal instruction detection on extension words of any instruction,
including MOVEC. Attempting to execute an instruction with an illegal extension word causes undefined
results.
3.5.4
Attempted division by zero causes an exception (vector 5, offset = 0x014) except when the PC points to
the faulting instruction (DIVU, DIVS, REMU, REMS).
3.5.5
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. Refer to the ColdFire Programmer’s Reference Manual for lists of supervisor- and
user-mode instructions.
3.5.6
To aid in program development, the CF2 processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by the assertion of the T bit in the status register (SR[15] = 1),
the completion of an instruction execution signals a trace exception. This functionality allows a debugger
to monitor program execution.
The single exception to this definition is the STOP instruction. When the STOP opcode is executed, the
processor core waits until an unmasked interrupt request is asserted, then aborts the pipeline and initiates
interrupt exception processing.
3-10
Address Error Exception
Illegal Instruction Exception
Divide By Zero
Privilege Violation
Trace Exception
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor