MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 252

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

UART Modules
15.3.2.1
The transmitter is enabled through the UART command register (UCR) located within the UART module.
The UART module signals the CPU when it is ready to accept a character by setting the transmitter-ready
bit (TxRDY) in the UART status register (USR). Functional timing information for the transmitter is
shown in
The transmitter converts parallel data from the CPU to a serial bit stream on TxD. It automatically sends
a start bit followed by:
The least significant bit is sent first. Data is shifted from the transmitter output on the falling edge of the
clock source.
After the transmission of the stop bits, if a new character is not available in the transmitter holding register,
the TxD output remains in the high (mark condition) state, and the transmitter-empty bit (TxEMP) in the
USR is set. Transmission resumes and the TxEMP bit is cleared when the CPU loads a new character into
the UART transmitter buffer (UTB). If the transmitter receives a disable command, it continues operating
until the character (if one is present) in the transmit-shift register is completely shifted out of transmitter
15-6
.
•
•
•
The programmed number of data bits
An optional parity bit
The programmed number of stop bits
Figure
EXTERNAL INTERFACE
Transmitter
TRANSMIT
BUFFER (UTB)
(2 REGISTERS)
15-5.
Figure 15-4. Transmitter and Receiver Functional Diagram
(4 REGISTERS)
RECEIVE
BUFFER (URB)
RECEIVER HOLDING REGISTER 1
UART MODE REGISTER 1 (UMR1)
UART MODE REGISTER 2 (UMR2)
MCF5253 Reference Manual, Rev. 1
UART COMMAND REGISTER (UCR)
UART STATUS REGISTER (USR)
TRANSMIT HOLDING REGISTER
RECEIVER HOLDING REGISTER 2
TRANSMIT SHIFT REGISTER
UART SERIAL CHANNEL
RECEIVER HOLDING REGISTER 3
RECEIVER SHIFT REGISTER
W
R/W
R
R
R/W
W
FIFO
Freescale Semiconductor
RXD
TXD