MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 162

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
The SWT can be enabled or disabled using the SWE bit in the SYPCR. If enabled, the SWT requires the
execution of a software watchdog servicing sequence periodically. If this periodic servicing action does
not occur, the SWT times-out resulting in a SWT IRQ or hardware reset, as programmed by the SWRI bit
in the SYPCR.
If the SWT times out and the software watchdog transfer acknowledge enable (SWTA = SYPCR[2]) bit is
set in the system protection control register, the SWT IRQ will assert. If after another timeout and the SWT
IACK cycle has not occurred, the SWT TA signal will assert in an attempt to terminate the bus cycle and
allow IACK cycle to proceed. The setting of the SWTAVAL flag bit (SYPCR[1]) in the system protection
control register indicates that the SWT TA signal was asserted. The SWTA function when terminating a
locked bus is shown in
When the SWT times out and SWRI register bit is programmed for a software reset, an internal reset will
be asserted, and the SWTR register bit will be set in the RSR.
To prevent SWT from interrupting or resetting, users must service the SWSR register. The SWT service
sequence consists of the following steps:
9-18
1. Write $55 to SWSR
2. Write $AA to the SWSR
(BIT 1 IN SYPCR)
SWT IRQ
SWTAVAL
SWT TA
SWTA FUNCTIONALITY BY WRITING SYPCR
1
1
CODE ENABLES SWT INTERRUPT AND
2
1 SWT IRQ AND SWT TA ARE ACTIVE-LOW signals.
2 SWTAVAL IS SET TO ‘1’ IF SWT TA SIGNAL is ASSERTED.
Figure
Figure 9-10. MCF5253 Unterminated Access Recovery
2. UNABLE TO SERVICE SWT INTERRUPT DUE TO “HUNG” BUS
PROBLEM:
SWT TIMEOUT
CYCLE. WAIT ANOTHER SWT TIMEOUT BEFORE setTING SWTA.
1. SWT TIMES-OUT DUE TO UN-TERMINATED BUS
9-10.
MCF5253 Reference Manual, Rev. 1
NOTE: RECOMMEND THAT SWT IRQ
BE SET TO THE HIGHEST LEVEL IN THE SYSTEM.
SWT TIMEOUT
3. HELD UNTIL ANOTHER
BUS CYCLE STARTS
CODE IN SWT INTERRUPT HANDLER POLLS THE
SWTAVAL BIT IN THE SYPCR TO DETERMINE
WHETHER OR NOT SWT TA WAS NEEDED.
IF SO, EXECUTE CODE TO IDENTIFY BAD ADDRESS.
SWT IACK CYCLE
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