MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 275

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

15.4.17 Programming
Figure 15-23
The routines are divided into these three categories:
15.4.17.1 UART Module Initialization
The UART module initialization routines consist of SINIT and CHCHK. SINIT is called at system
initialization time to check UART operation. Before SINIT is called, the calling routine allocates two
words on the system stack. On return to the calling routine, SINIT passes information on the system stack
to reflect the status of the UART. If SINIT finds no errors, the receiver and transmitter are enabled. The
CHCHK routine performs the actual checks as called from the SINIT routine. When called, SINIT places
the UART in the local loopback mode and checks for the following errors:
15.4.17.2 I/O Driver Example
The I/O driver routines consist of INCH and OUTCH. INCH is the terminal input character routine and
obtains a character from the receiver. OUTCH sends a character to the transmitter.
15.4.17.3 Interrupt Handling
The interrupt-handling routine consists of SIRQ, which is executed after the UART module generates an
interrupt caused by a change in break (beginning of a break). SIRQ then clears the interrupt source, waits
for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from
exception processing to the system monitor.
Freescale Semiconductor
Address MBAR + $1FC (UOP00)
Reset
1. UART Module Initialization
2. I/O Driver
3. Interrupt Handling
•
•
•
•
W
R
Transmitter Never Ready
Receiver Never Ready
Parity Error
Incorrect Character Received
MBAR + $23C (UOP01)
MBAR2 + $C3C (UOP02)
shows the basic interface software flowchart required for operation of the UART module.
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7
–
6
Figure 15-22. Output Port Data Registers (UOP0n)
MCF5253 Reference Manual, Rev. 1
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5
–
4
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3
–
2
Access: User write only
1
–
UART Modules
RTS
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0
15-29