MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 152

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

System Integration Module (SIM)
Table 9-8
this table can be any internal interrupt source programmed to the given level and priority. For example,
assume that two internal interrupt sources were programmed to IL[2:0] =110, one having a priority of
IP[1:0] = 01 and one having a priority of IP[1:0] = 10. If both assert an interrupt request at the same time,
the order of servicing would occur as follows:
9-8
Address See Memory Map
AVEC
Reset
Field
6–5
4–2
1–0
1. Internal module with IL[2:0] =110 and IP[1:0] = 10 would be serviced first
2. Internal module with IL[2:0] = 110 and IP[1:0] = 01 would be serviced last
IL
IP
7
W
R
shows all possible primary source priority schemes for the MCF5253. The interrupt source in
The Autovector Enable bit determines whether the interrupt-acknowledge cycle requires an autovector response (for
the internal interrupt level indicated in IL[2:0] for each interrupt).
0 Interrupting source returns vector during interrupt-acknowledge cycle
1 SIM generates auto vector during interrupt acknowledge cycle
Reserved.
The Interrupt Level bits indicate the interrupt level assigned to each interrupt input.
The Interrupt Priority bits indicate the interrupt priority within the interrupt level assignment.
priority levels associated with the IP contents.
AVEC
0
7
Interrupt Level
7
7
Table 9-6. Interrupt Control Register (ICR) Field Descriptions
Table 9-5
–
6
Figure 9-4. Interrupt Control Register (ICR)
IL[2:0]
Table 9-7. Interrupt Priority Assignment
111
111
Table 9-8. Interrupt Priority Scheme
IP[1:0]
MCF5253 Reference Manual, Rev. 1
–
5
00
01
10
11
Internal Module ICR Reg
IP[1]
IL[2]
1
1
0
4
Description
Priority
Higher
Lower
High
Low
IL[1]
IP[0]
0
3
1
0
IL[0]
Interrupt Source
Internal Module
Internal Module
0
2
Freescale Semiconductor
Access: User read/write
IP[1]
Table 9-7
0
1
shows the
IP[0]
0
0