MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 592

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Universal Serial Bus Interface
It is the responsibility of the DCD to maintain a state variable to differentiate between the DefaultFS/HS
state and the Address/Configured states. Change of state from Default to Address and the Configured
states is part of the enumeration process described in the USB 2.0 Specification, Chapter 9, Device
Framework.
As a result of entering the Address state, the device address register (DEVICEADDR) must be
programmed by the DCD.
Entry into the Configured indicates that all endpoints to be used in the operation of the device have been
properly initialized by programming the ENDPTCTRLn registers and initializing the associated queue
heads.
24.11.2.1 Bus Reset
A bus reset is used by the host to initialize downstream devices. When a bus reset is detected, the
USB_controller will renegotiate its attachment speed, reset the device address to 0, and notify the DCD by
interrupt (assuming the USB Reset Interrupt Enable is set). After a reset is received, all endpoints (except
endpoint 0) are disabled and any primed transactions will be cancelled by the device controller. The
concept of priming will be clarified below, but the DCD must perform the following tasks when a reset is
received:
Read the reset bit in the PORTSCn register and make sure that it is still active. A USB reset will occur for
a minimum of 3 ms and the DCD must reach this point in the reset cleanup before end of the reset occurs,
otherwise a hardware reset of the device controller is recommended (rare.)
Free all allocated dTDs because they will no longer be executed by the device controller. If this is the first
time the DCD is processing a USB reset event, then it is likely that no dTDs have been allocated.
At this time, the DCD may release control back to the OS because no further changes to the device
controller are permitted until a Port Change Detect is indicated.
24-130
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•
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Clear all setup token semaphores by reading the ENDPTSETUPSTAT register and writing the same
value back to the ENDPTSETUPSTAT register.
Clear all the endpoint complete status bits by reading the ENDPTCOMPLETE register and writing
the same value back to the ENDPTCOMPLETE register.
Cancel all primed status by waiting until all bits in the ENDPTPRIME are 0 and then writing
0xFFFF_FFFF to ENDPTFLUSH.
A hardware reset can be performed by writing a one to the USB_DR reset bit in the USBCMD
reset. Note: a hardware reset will cause the device to detach from the bus by clearing the Run/Stop
bit. Thus, the DCD must completely re-initialize the USB_DR after a hardware reset.
USB Reset Received
Port Change Detect
High-Speed Port
DCSuspend
Table 24-80. Device Controller State Information Bits
Bit
MCF5253 Reference Manual, Rev. 1
PORTSC
Register
USBSTS
USBSTS
USBSTS
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