MCF5253CVM140J Freescale Semiconductor, MCF5253CVM140J Datasheet - Page 255

• Manufacturer Part Number: MCF5253CVM140J
• Description: IC MCU 2.1MIPS 140MHZ 225MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Processor Series: MCF525x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

UART Modules
framing error (FE), overrun error (OE), and received break (RB) conditions (if any) set error and break
flags in the USR at the received character boundary and are valid only when the RxRDY bit in the USR is
set.
If a break condition is detected (RxD is low for the entire character including the stop bit), a character of
all zeros is loaded into the receiver holding register and the Receive Break (RB) and RxRDY bits in the
USR are set. The RxD signal must return to a high condition for at least one-half bit time before a search
for the next start bit begins.
The receiver will detect the beginning of a break in the middle of a character if the break persists through
the next character time. When the break begins in the middle of a character, the receiver places the
damaged character in the receiver first-in-first-out (FIFO) stack and sets the corresponding error
conditions and RxRDY bit in the USR. The break persists until the next character time, the receiver places
an all-zero character into the receiver FIFO, and sets the corresponding RB and RxRDY bits in the USR.
Interrupts can be enabled on receive break.
15.3.2.3
Receiver FIFO
The FIFO is used in the UART receiver buffer logic. The FIFO consists of three receiver holding registers.
The receive buffer consists of the FIFO and a receiver shift register connected to the RxD (refer to
Figure
15-4). Data is assembled in the receiver shift register and loaded into the top empty receiver holding
register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple buffered.
In addition to the data byte, three status bits, parity error (PE), framing error (FE), and received break (RB)
are appended to each data character in the FIFO; overrun error (OE) is not appended. By programming the
error-mode bit (ERR) in the channel's mode register (UMR1), status can be provided in character or block
modes.
The RxRDY bit in the USR is set whenever one or more characters are available to be read by the CPU.
A read of the receiver buffer produces an output of data from the top of the FIFO. After the read cycle, the
data at the top of the FIFO and its associated status bits are ‘'popped,'’ and the receiver shift register can
add new data at the bottom of the FIFO. The FIFO-full status bit (FFULL) is set if all three stack positions
are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt.
Character and block modes are two error modes that can be selected within the UMR.
In the character mode, status provided in the USR is given on a character-by-character basis and thus
applies only to the character at the top of the FIFO. In the block mode, the status provided in the USR is
the logical OR of all characters coming to the top of the FIFO since the last reset error command. A
continuous logical OR function of the corresponding status bits is produced in the USR as each character
reaches the top of the FIFO.
The block mode is useful in applications where the software overhead of checking each character's error
cannot be tolerated. In this mode, entire messages are received and only one data integrity check is
performed at the end of the message. This mode has a data-reception speed advantage; however, each
character is not individually checked for error conditions by software. If an error occurs within the
message, the error is not recognized until the final check is performed, and no indication exists as to which
message character is at fault.
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
15-9