MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 

Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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H.5.1
Erased EPROM verification
If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see
Figure H-3
and
Figure
green LED be turned on. PD1 is then checked. If PD1=0, the bootstrap program stops here and
no programming occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap
program proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then
checked for complete erasure; if any EEPROM byte is not erased, the program will stop before
erasing the SEC byte. When both EPROM and EEPROM1 are completely erased and the security
bit is cleared the programming operation can be performed. A schematic diagram of the circuit
required for erased EPROM verification is shown in
H.5.2
EPROM/EEPROM parallel bootstrap
Within this mode there are various subsections which can be utilised by correctly configuring the
port pins shown in
Table
The erased EPROM verification program will be executed first as described in
When PD2=0, the programming time is set to 5 milliseconds with the bootstrap program and verify
for the EPROM taking approximately 15 seconds. The EPROM will be loaded in increasing
address order with non EPROM segments being skipped by the loader. Simultaneous
programming is performed by reading sixteen bytes of data before actual programming is
performed, thus dividing the loading time of the internal EPROM by 16. If any block of 16 EPROM
bytes or 1 EEPROM byte of data is in the erased state, no programming takes place, thus
speeding up the execution time.
Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4
and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,
handshake will be provided by PC5 and PC6 according to the timing diagram of
also
Figure
H-6).
During programming, the green LED will flash at about 3 Hz.
Upon completion of the programming operation, the EPROM and EEPROM1 content will be
checked against the external data source. If programming is verified the green LED will stay on,
while an error will cause the red LED to be turned on.
circuit which can be used to program the EPROM or to load and execute data in the RAM.
Note:
The entire EPROM and EEPROM1 can be loaded from the external source; if it is
desired to leave a segment undisturbed, the data for this segment should be all $00s
for EPROM data and all $FFs for EEPROM1 data.
14
Freescale
H-16
H-4). Only when the whole EPROM content is verified as erased will the
Figure
H-4.
MC68HC705B32
H-7.
Section
Figure H-5
Figure H-7
is a schematic diagram of a
MC68HC05B6
Rev. 4.1
H.5.1.
(see