MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits that are shown shaded in the above representation are explained individually
in the relevant sections of this manual. The complete register plus an explanation of
each bit can be found in
7.2
PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous
register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no
effect on the D/A converters’ 8-bit resolution (see
f
÷2
OSC
7
÷32
7.3
PLM during STOP mode
On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is
exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by
power-on or external reset the registers values are forced to $00.
7.4
PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
Freescale
7-4
Section 3.8
Figure
Bus
SM bit = 0
frequency (f
)
OP
÷4
SM bit = 1
Figure 7-3 PLM clock selection
PULSE LENGTH D/A CONVERTERS
7-3).
Timer
SF bit = 1
clock
x4096
SF bit = 0
x256
MC68HC05B6
Rev. 4.1
PLM
clock