MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 86

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
6.11.3
Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
SCI control (SCCR2)
TIE — Transmit interrupt enable
1 (set)
TDRE interrupts enabled.
0 (clear) –
TDRE interrupts disabled.
TCIE — Transmit complete interrupt enable
6
1 (set)
TC interrupts enabled.
0 (clear) –
TC interrupts disabled.
RIE — Receiver interrupt enable
1 (set)
RDRF and OR interrupts enabled.
0 (clear) –
RDRF and OR interrupts disabled.
ILIE — Idle line interrupt enable
1 (set)
IDLE interrupts enabled.
0 (clear) –
IDLE interrupts disabled.
TE — Transmitter enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and
the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M
(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software
sets the TE bit from a cleared state.
If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the
present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high
impedance state.
If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,
the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new
preamble. After this latest transmission, and provided the TDRE bit is set (no new data to
transmit), the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs.
This function allows the user to neatly terminate a transmission sequence.
Freescale
6-14
Address
bit 7
bit 6
bit 5
bit 4
$000F
TIE
TCIE
RIE
ILIE
SERIAL COMMUNICATIONS INTERFACE
State
bit 3
bit 2
bit 1
bit 0
on reset
TE
RE
RWU
SBK
0000 0000
MC68HC05B6
Rev. 4.1

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